初始化BRAM警告coe文件不存在

你好@ zzhcwj1992
看起来BMG IP与IP打包器的打包引起了问题。
打开IP打包程序项目并检查COE文件是否填充在component.xml文件中的“文件组”下。
如果它不存在，请尝试将其添加到文件组部分。
我建议您使用xpm_memory宏而不是BMG IP，您可以在其中提供mem文件作为输入。
请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug953-vivado-7series-libraries.pdf的第2章。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @zzhcwj1992
 
It looks like the packaging of the BMG IP with IP packager is causing problem. Open the IP packager project and check if the COE file is populated under "file groups" in component.xml file. If it is not present try adding it to file groups section.
 
I would suggest you to use xpm_memory macro instead of BMG IP where you can provide mem file as input. Refer to chapter-2 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug953-vivado-7series-libraries.pdf
Thanks,
Deepika.
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你好@ vemulad
我打开“文件组”并选择“合并文件”。
tran50_b.coe有错误，错误是“找不到coe文件”。



以下为原文

Hi @vemulad
 
I open the "file groups" and choose "merge files". there is an error for tran50_b.coe and the error is "cannot find coe file". 

你好@ zzhcwj1992
在快照中，coe文件在verilog sysnthesis部分中显示两次。
尝试删除这两个文件，并使用右键菜单中的选项手动添加COE文件。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi @zzhcwj1992


Inthe snapshot, the coe file is shown twice in verilog sysnthesis section. Try removing both these files and manually add the COE file using option in right click menu.
Thanks,
Deepika.
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