在PCS环回模式下,如果没有从TXP / TXN到RXP / RXN的连接,则CDR的RXRECCLK输出预计不会好。
这是由于输入锁定时缺少数据转换。
如果设计需要RXRECCLK用于其结构逻辑,则设计可能会失败。
对于这些设计,建议在“锁定到参考”模式下使用CDR。按照以下步骤确保CDR处于“锁定到参考”模式:步骤1:驱动以下信号设置RXOUTCLKSEL以选择RXOUTCLKPCS,(或
)将RXCDRHOLD设置为1'b1并将RXCDROVRDEN设置为1'b0步骤2:对收发器执行完全RX复位GTRXRESETIf设计不使用RXRECCLK用于结构逻辑,仅需要步骤2。
谢谢和RegardsBalkrishan -----------------------------------------------
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以上来自于谷歌翻译
以下为原文
In PCS loopback mode, if there is no connection from TXP/TXN to RXP/RXN, then RXRECCLK output from CDR is not expected to be good.
This is due to a lack of data transitions at the input to lock to.
If a design requires RXRECCLK for its fabric logic, the design can fail.
For these designs, it is recommended to use CDR in "lock to reference" mode.
Follow the steps below to make sure that the CDR is in "lock to reference" mode:
Step1: Drive the following signals
Set RXOUTCLKSEL to select RXOUTCLKPCS,
(OR)
Set RXCDRHOLD to 1'b1 and RXCDROVRDEN to 1'b0
Step2: Perform a full RX reset of the transceiver
Pulse GTRXRESET
If a design does not use RXRECCLK for fabric logic, only Step 2 is required.Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
在PCS环回模式下,如果没有从TXP / TXN到RXP / RXN的连接,则CDR的RXRECCLK输出预计不会好。
这是由于输入锁定时缺少数据转换。
如果设计需要RXRECCLK用于其结构逻辑,则设计可能会失败。
对于这些设计,建议在“锁定到参考”模式下使用CDR。按照以下步骤确保CDR处于“锁定到参考”模式:步骤1:驱动以下信号设置RXOUTCLKSEL以选择RXOUTCLKPCS,(或
)将RXCDRHOLD设置为1'b1并将RXCDROVRDEN设置为1'b0步骤2:对收发器执行完全RX复位GTRXRESETIf设计不使用RXRECCLK用于结构逻辑,仅需要步骤2。
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。
以上来自于谷歌翻译
以下为原文
In PCS loopback mode, if there is no connection from TXP/TXN to RXP/RXN, then RXRECCLK output from CDR is not expected to be good.
This is due to a lack of data transitions at the input to lock to.
If a design requires RXRECCLK for its fabric logic, the design can fail.
For these designs, it is recommended to use CDR in "lock to reference" mode.
Follow the steps below to make sure that the CDR is in "lock to reference" mode:
Step1: Drive the following signals
Set RXOUTCLKSEL to select RXOUTCLKPCS,
(OR)
Set RXCDRHOLD to 1'b1 and RXCDROVRDEN to 1'b0
Step2: Perform a full RX reset of the transceiver
Pulse GTRXRESET
If a design does not use RXRECCLK for fabric logic, only Step 2 is required.Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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