大家好,在我将两个ref时钟连接到CPLL和QPLL NORTHREFCLK之后,设计通过了比特流生成。所以我尝试通过经验和UG476.1确认以下理解。
当只需要一个参考时钟,即使时钟来自另一个四核,它仍然可以与CPLL和QPLL中的GTREFCLK_IN连接,正确?2。
当我需要两个参考时钟时,它们都来自另一个四核,我必须根据银行位置将它们连接到CPLL,QPLL中的NORTH或SOUTH CLK_IN,对吗?我的另一个问题是,如果时钟来自MGTREF_CLK0引脚
,我是否必须在CPLL和QPLL中连接GTREFCLK0,或者我可以将它交换到GTREFCLK1?谢谢。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Hello all,
After I connect two ref clocks to both CPLL and QPLL NORTHREFCLK, then the design pass the bitstream generation.
So I try to confirm following understanding from experience and from UG476.
1. WhenIonly need one ref clock, even the clock come from another quad, it can still be connected with GTREFCLK_IN in CPLL and QPLL, correct?
2. When I need two ref clocks, both of them come from another quad, I have to connect them with NORTH or SOUTH CLK_IN in CPLL, QPLL, based on bank location, correct?
Another question I have is, if the clock comes from MGTREF_CLK0 pin, do I have to connect with GTREFCLK0 in CPLL and QPLL, or I can swap it to GTREFCLK1?
Thank you.View solution in original post
大家好,在我将两个ref时钟连接到CPLL和QPLL NORTHREFCLK之后,设计通过了比特流生成。所以我尝试通过经验和UG476.1确认以下理解。
当只需要一个参考时钟,即使时钟来自另一个四核,它仍然可以与CPLL和QPLL中的GTREFCLK_IN连接,正确?2。
当我需要两个参考时钟时,它们都来自另一个四核,我必须根据银行位置将它们连接到CPLL,QPLL中的NORTH或SOUTH CLK_IN,对吗?我的另一个问题是,如果时钟来自MGTREF_CLK0引脚
,我是否必须在CPLL和QPLL中连接GTREFCLK0,或者我可以将它交换到GTREFCLK1?谢谢。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Hello all,
After I connect two ref clocks to both CPLL and QPLL NORTHREFCLK, then the design pass the bitstream generation.
So I try to confirm following understanding from experience and from UG476.
1. WhenIonly need one ref clock, even the clock come from another quad, it can still be connected with GTREFCLK_IN in CPLL and QPLL, correct?
2. When I need two ref clocks, both of them come from another quad, I have to connect them with NORTH or SOUTH CLK_IN in CPLL, QPLL, based on bank location, correct?
Another question I have is, if the clock comes from MGTREF_CLK0 pin, do I have to connect with GTREFCLK0 in CPLL and QPLL, or I can swap it to GTREFCLK1?
Thank you.View solution in original post
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