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[问答]

KIntex 7 GTX是否可以使用相邻四边形的两个参考时钟?

我正在研究一种我喜欢Xilinx EVB KC705的设计。
我尝试使用LPC FMC连接。
LPC中的GTX处于四通道117,而与LPC连接的ref时钟是四通道116 ref clock 1(基于原理图)。在我的设计中,我需要两个116的ref时钟用于四通道117中的MGT3。然后在我的
设计我在比特流生成阶段有错误,它是:
设计没有完成路由,错误发生在两个ref时钟。
在这种情况下,我想知道KIntex 7 GTX是否可以使用相邻四边形的两个参考时钟?
根据我的理解,我知道GTX可以使用相邻四极杆的参考时钟,但我不确定使用两个时钟是否可行。
提前致谢。

以上来自于谷歌翻译


以下为原文

I am working on a design whcih I amusing Xilinx EVB KC705. I try to use the LPC FMC connect. The GTX in LPC is in quad 117 while the ref clocks connect with LPC is in quad 116 ref clock 1 (based on schematic).In my design, I need both ref clock from quad 116 for the MGT3 in quad 117. Then in my design I have error in bitstream generation stage which is :
design is not completed routed, the errors happen in two ref clocks.

In this case, I wonder whether KIntex 7 GTX can use both two ref clocks from adjacent quad? Based on my understanding, I know GTX can use the ref clock from adjacent quad, but I am not sure whether using two clocks is feasible or not.

Thanks in advance.

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李凤英

2019-4-4 19:20:57
大家好,在我将两个ref时钟连接到CPLL和QPLL NORTHREFCLK之后,设计通过了比特流生成。所以我尝试通过经验和UG476.1确认以下理解。
当只需要一个参考时钟,即使时钟来自另一个四核,它仍然可以与CPLL和QPLL中的GTREFCLK_IN连接,正确?2。
当我需要两个参考时钟时,它们都来自另一个四核,我必须根据银行位置将它们连接到CPLL,QPLL中的NORTH或SOUTH CLK_IN,对吗?我的另一个问题是,如果时钟来自MGTREF_CLK0引脚
,我是否必须在CPLL和QPLL中连接GTREFCLK0,或者我可以将它交换到GTREFCLK1?谢谢。
在原帖中查看解决方案

以上来自于谷歌翻译


以下为原文

Hello all,

After I connect two ref clocks to both CPLL and QPLL NORTHREFCLK, then the design pass the bitstream generation.

So I try to confirm following understanding from experience and from UG476.
1. WhenIonly need one ref clock, even the clock come from another quad, it can still be connected with GTREFCLK_IN in CPLL and QPLL, correct?

2. When I need two ref clocks, both of them come from another quad, I have to connect them with NORTH or SOUTH CLK_IN in CPLL, QPLL, based on bank location, correct?

Another question I have is, if the clock comes from MGTREF_CLK0 pin, do I have to connect with GTREFCLK0 in CPLL and QPLL, or I can swap it to GTREFCLK1?

Thank you.View solution in original post
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贾佳斌

2019-4-4 19:31:51
可以路由来自相邻四边形的两个REFCLK。
请尝试使用GT向导正确设置时钟。
--------------------------------------------------
----------------------------别忘了回复,给予kudo并接受为解决方案---------
--------------------------------------------------
-------------------

以上来自于谷歌翻译


以下为原文

Both REFCLK's from adjacent quad can be routed. Please try to use GT wizard to setup the clocking properly.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
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王慕涛

2019-4-4 19:44:16
嗨,
您是否可以共享您看到错误的设计,以便我可以查看错误的原因是什么?

以上来自于谷歌翻译


以下为原文

Hi,
 
Is it possible for you to share the design in which you see the error so taht i can have a look on what could be the reason for the error?
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李凤英

2019-4-4 20:02:23
感谢您的回复。
在我的设计中,我手动实例化了QPLL。
我想知道,因为ref时钟来自相邻的四核,我应该把时钟驱动到GTNORTHREFCLK还是GTSOUTHREFCLK?基于芯片,时钟来自116银行,而GT在117银行,时钟低于GT,在
这种情况,我应该把时钟驱动到北方吗?谢谢。

以上来自于谷歌翻译


以下为原文

Thank you for reply. In my design, I instantiated the QPLL manually. I wonder since the ref clocks come from adjacent quad, should I driven the clock into the GTNORTHREFCLK or GTSOUTHREFCLK?

Based on the chip, the clock come from 116 bank while the GT is in 117 bank, the clock is below of the GT, in this case, should I driven the clock to North?

Thank you.
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