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[问答]

用于AD7626的Virtex-6 lm605板的LVDS时钟不起作用

大家好
我的名字是fang,我正在连接ADC板(AD7626)和ml605套件。
ADC具有16位LVDS,10Msps输出。
我使用ml605 Gclk引脚向AD7626输出20M时钟,它工作,上升沿为16 ns,但当时钟变为80M时,它不起作用.ADC的时钟拓扑结构为:
DCM + BUFG + ODDR + OBUFDS
80M波形如下所示,表明边缘太慢而无法产生这样的时钟?

以上来自于谷歌翻译


以下为原文

hello everbody
My name is fang and I am interfacing a ADC board(AD7626) to ml605 kit. The ADC has a 16bit LVDS,10Msps output.
I used ml605 Gclk pin to output 20M clock to AD7626,it works,the rising edge is 16 ns,but when the clock changed to 80M,it does not work.the clock topology for ADC is:
DCM+BUFG+ODDR+OBUFDS
80M waveform show as follows,it shows that the edge is too slow and it can not generate such clock?

回帖(1)

潘晶燕

2019-4-3 16:43:15
F,
你使用什么IO标准?
电缆有多长?
什么是阻抗?
发送端的信号是什么样的?
电缆的损耗是多少?
您是否进行了信号完整性分析?
它是什么样子的?
通常,与电缆的阻抗匹配输出导致最佳信号完整性。
LVCMOS 8 mA约为50欧姆,因此使用具有快速压摆率的标准应该可以轻松地在数米的50欧姆同轴电缆上提供80 MHz时钟。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

f,
 
What IO standard are you using?  How long is the cable?  What is the impedance?  What does the signal look like at the transmit end?  What is the loss of the cable?  Have you performed a signal integrity analysis? What does it look like?
 
In general, an impedance matched output to the cable results in the best signal integrity.  LVCMOS 8 mA is approximately 50 ohms, so use of that standard, with fast slew rate should easily provide a 80 MHz clock over many meters of a good 50 ohm coaxial cable.
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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