如果时钟边沿和输出不对齐会发生什么？

你是如何确定两个信号没有对齐的？
您必须意识到输出触发器和到达器件引脚的实际信号存在一定的传输延迟。
有几种方法：
1.你可以将输出触发器限制在器件引脚的IOB中（我猜你有一个LOC约束）。
这提供了来自输出FF和器件引脚的最小路由延迟量。
2.您可以使用OFFSET = OUT约束约束输出网络。
您应该阅读Timing Closure指南以获取详细信息。
为什么这对你来说是一个问题？
时钟是否与数据一起传输？
如果是这样，则上述OFFSET约束可以与转发时钟的引用一起使用。
然后，这些工具将满足您指定的与所需时钟（而不是FPGA系统时钟）相关的输出时序。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

How are you determining that the two signals are not aligned?
 
You must be aware that there is a certain amount of transmission delay from the output flipflop and the actual signal arriving at the device pin.
 
There are a couple of approaches:
 
1. You can constrain the output flipflop to be in the IOB of the device pin (for which you have a LOC constraint, I suppose). This provides the smallest amount of routing delay from the output FF and the device pin.
2. You can constrain the output net with the OFFSET = OUT constraint. You should read the Timing Closure guide for detailed information.
 
Why is this an issue for you? Is the clock to be transmitted with the data? If so, the above OFFSET constraint can be used with a reference to the forwarded clock. The tools will then work to meet the output timing you specify in relation to the required clock (rather than the FPGA system clock).
 
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"That which we must learn to do, we learn by doing." - Aristotle

你好，只是小修正。
您可以使用IOB属性，以便工具自动将所有输出FF分配给IO站点以获得更好的性能。谢谢，Yash



以下为原文

Hello,

Just small correction. You can use IOB attribute so that tool will automatically assign all output FF to the IO sites for better performance.

Thanks,
Yash