赛灵思
直播中

胡雄相

7年用户 158经验值
私信 关注
[问答]

怎么从VHDL更新Microblaze BRAM

我有一个带有64kb BRAM的Microblaze,带有指令和数据空间(一个端口上的标准I和另一个端口上的D)。
我有另一个64kb只在一个端口上连接到Microblaze并且只包含数据。
第二个端口将由自定义VHDL代码写入。
第二个BRAM地址在Microblaze上为0x00010000。
在导出BRAM的第二个端口以供自定义VHDL代码使用之后,我对VHDL端的BRAM地址感到有些困惑。
BRAM的第一个位置是VHDL侧0x00000000吗?
还是0x00010000?
在我看来,VHDL方面不知道如何在MicroBlaze端配置BRAM。
我也意识到(至少我认为是这种情况)是64kb BRAM是几个物理BRAM。
本地内存总线控制器似乎通过将内存请求映射到正确的BRAM来处理这个问题。
但是,VHDL方面并不清楚(我怀疑它不是这样)。
您是否必须在VHDL端处理单个物理BRAM。
提前致谢,
BB

以上来自于谷歌翻译


以下为原文

I have a Microblaze with 64kb BRAM with instruction and data space (standard I on one port and D on the other port).  I have another 64kb that is only connected to the Microblaze on one port and will only contain data.  The second port will be written to by custom VHDL code.  The second BRAM address is at 0x00010000 on the Microblaze.  After exporting the second port of the BRAM to be used by the custom VHDL code, I'm a bit confused as to the address of the BRAM on the VHDL side.  Is the first location of the BRAM on the VHDL side 0x00000000?  or is it 0x00010000?  It seems to me that the VHDL side doesn't know about how the BRAM is configured on the MicroBlaze side.  I also realize (at least I think this is the case) is that the 64kb BRAM is actaully several physical BRAMs.  The local memory bus controller seems to take care of this by mapping memory requests to the correct BRAM.  However, it's not clear how (and I suspect that it isn't) on the VHDL side.  Do you have to deal with individual physical BRAMs on the VHDL side.

Thanks in advance,
bb

回帖(12)

李裕伦

2019-3-4 12:25:13
请检查您是否遵循此操作,然后您可以在自定义IP中将其用作RTL中的单独BRAM。
http://www.xilinx.com/support/answers/52063.html

以上来自于谷歌翻译


以下为原文

Please check if you are following this and then you can use this in the custom ip as separate BRAMs in your RTL.
http://www.xilinx.com/support/answers/52063.html
举报

孙缅禧

2019-3-4 12:35:20
我确实按照您附加的应用笔记进行内存分配。
这一切似乎都很好。
分配给VHDL代码共享的64kb内存位于Microblaze端的地址0x00010000。
我的问题是VHDL方面BRAM中第一个位置的地址是什么?
我相信它是0x00000000,而我的一些同事认为它是0x00010000(即Microblaze方面的相同地址)。
BB

以上来自于谷歌翻译


以下为原文

I am indeed doing the memory allocation per the app note that you attached.  That all seems to work fine.  The 64kb memory allocated to be shared with VHDL code is at address 0x00010000 on the Microblaze side.  My question is what is the address of the first location in the BRAM on the VHDL side?  I believe it to be 0x00000000 while some of my colleagues believe that it is 0x00010000 (i.e., the same address on the Microblaze side).
 
bb
举报

张丽丽

2019-3-4 12:43:43
一种解决方案是将您的IP(自定义逻辑)作为AXI主机,可以在总线上启动AXI读取。
因此,它可以访问与Microblaze相同的地址空间。
在这种情况下,BRAM起始地址将为0x00010000。
要了解如何创建自定义AXI母版,您可以参考以下AR:http://www.xilinx.com/support/answers/37425.htm

以上来自于谷歌翻译


以下为原文

One solution is to make your IP (custom logic) as an AXI master which can initiate AXI reads on the bus. Thus, it can access the same address space as Microblaze does. In that case the BRAM starting address will be 0x00010000.

To learn how to create the custom AXI master, you can refer to the following AR:
http://www.xilinx.com/support/answers/37425.htm
举报

李裕伦

2019-3-4 12:49:10
是的,它与microblaze side.0x00010000上的地址相同

以上来自于谷歌翻译


以下为原文

Yes It is the same address on microblaze side. 0x00010000
举报

更多回帖

发帖
×
20
完善资料,
赚取积分