使用DCM如何生成奇数时钟频率？

Z，
1. DCM DFS合成M / D，其中M = 2到32，D =输入时钟频率的2到32倍。
如果这不是你希望的值，你需要在电路板上另一个晶体振荡器。
2.在详细模式下的布局和布线之后的报告详细说明了设计中使用的所有内容。
每个模块中的多少并不重要，因为在综合，放置和路由之后，您不知道共享，修剪等等，因此“模块使用”很有趣，但每个人需要的实际项目是“它是否适合
？”
您可以放置​​和布线单个模块（最小接口，因此它们不会被修剪），但它与最终结果不匹配（但它有点用处）。
Xilinx IP数据表确实列出了所列资源（例如：SEM IP核）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

z,
 
1.  The DCM DFS synthesizes M/D, where M = 2 to 32, and D=2 to 32 times the input clock frequency.
 
If that isn't spot on the value you wish, you will need another crystal oscillator on the board.
 
2.  The reports after place and route in the verbose mode detail absolutely everything that gets used in the design.  How much is in each module is not important, as after synthesis, place, and route, you have no idea what got shared, trimmed, etc. so "module usage" is interesting, but the actual item everyone needs is "does it fit?"
 
You could place and route individual modules (with minimum interfacing so they don't get trimmed), but it will not match the final results (but it is somewhat useful).  The Xilinx IP data sheets do have estimates of the resources listed (example:  SEM IP core).
 
 
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

zubin_kumar31写道：
1）奇数频率 - 使用DCM，它很容易产生100MHz，25MHz等频率。但是如何生成11.6MHz，13.2MHz等奇数时钟频率？
我可能需要什么原语？
要么使用以必要频率运行的振荡器，要么使用具有可以产生奇怪频率的分数PLL的设备。
----------------------------是的，我这样做是为了谋生。



以下为原文

zubin_kumar31 wrote:
 
1) Odd frequencies - Using DCMs, its easy to generate frequencies like 100MHz, 25MHz etc. But how can I generate an odd clock frequncies like 11.6MHz, 13.2MHz etc.? What primitives might I need for this?

Either use an oscillator which runs at the necessary frequency, or use a device which has a fractional PLL which can generate the oddball frequencies.
----------------------------Yes, I do this for a living.