如何使用良好的RTL设计实践进行修复

我得到的大多数文件都是针对ASIC的静态时序分析。
我发现静态时序分析对FPGA（而非ASIC）设计非常有帮助。
xilinx文档专注于他们的时序分析工具
如果你考虑一下，那是对的，也是可以理解的。
我正在寻找讨论时序分析概念的文档，如设置保持时间，偏斜，传输延迟，其他时序违规等，以及如何使用良好的RTL设计实践进行修复。
在设计阶段，在综合之前甚至在HDL实现之前，最有用的时序分析工具可能是数据路径框图。
正是在这个层面上，首先发现了设计中的关键路径。
下一级时序分析将是后综合，后映射 - 设计已经致力于特定技术的一个点。
祝你的搜索顺利。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Most of the documents that i am getting are for static timing analysis which are intended towards ASIC.
 
I find static timing analysis is quite helpful for FPGA (rather than ASIC) design.
 
xilinx documents are focused towards their timing analyser tool
 
Quite right, and quite understandable, if you think about it.
 
i am looking for documents which discuss the concepts of timing analysis such as setup hold time, skew, transport delay, other timing violation etc. and how to fix then using good RTL design practices.
 
At the design stage, before synthesis and even before HDL implementation, the most useful timing analysis tools might be a datapath block diagram.  It is at this level that critical paths in the design are first found.  The next level of timing analysis would be post-synthesis, post-mapping -- a point at which the design has already been committed to a specific technology.
 
Good luck with your search.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594
Austin Lesea主要工程师Xilinx San Jose



以下为原文

http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594
Austin Lesea
Principal Engineer
Xilinx San Jose