你的问题是广泛而含糊的，这是适当的广泛和模糊的答案：
设计中的所有内容都可能影响设计的运行频率，包括BRAM。
您可以实现一种设计，该设计使用90％的器件可用Block RAM，同时保持Block RAM的全带宽（工作时钟频率）。
如果你相当小心，这应该不难实现。
这在很大程度上取决于您的其他设计。
使用90％的片上Block RAM和仅有20％的CLB资源的设计可能不是“拥挤”设计。
如果使用80％的CLB资源，则可能难以保持接近Block RAM的最大工作频率的工作时钟频率。
您设计的预期时钟频率是多少？
不要忽略CLB之间以及CLB和BRAM之间的互连延迟。
您在高带宽系统设计方面的经验如何，尤其是数据通路和流水线？
如果您有兴趣接近所选设备的工作频率限制，您的技能和才能将影响您的结果。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Your question is broad and vague, and here is the appropriate broad and vague answer:
Everything in your design may affect the operating frequency of your design, including the BRAMs.
You
can implement a design which uses 90% of the devices's available Block RAM while maintaining the full bandwidth (operating clock frequency) of the Block RAMs. If you are reasonably careful, this should not be difficult to achieve. This depends heavily on the rest of your design.
A design which uses 90% of the on-chip Block RAM and only 20% of the CLB resources is probably NOT a 'congested' design. If 80% of the CLB resources are utilised, you might have considerable difficulty maintaining an operating clock frequency which approaches the max operating frequency of the Block RAM.
What is the expected clock frequency for your design? Don't overlook the interconnect delays between CLBs, and between CLBs and BRAMs.
How experienced are you in high-bandwidth system design, especially datapaths and pipelines? Your skills and talents will affect your outcome, if you are interested in approaching the operating frequency limits of your selected device.
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post
你的问题是广泛而含糊的，这是适当的广泛和模糊的答案：
设计中的所有内容都可能影响设计的运行频率，包括BRAM。
您可以实现一种设计，该设计使用90％的器件可用Block RAM，同时保持Block RAM的全带宽（工作时钟频率）。
如果你相当小心，这应该不难实现。
这在很大程度上取决于您的其他设计。
使用90％的片上Block RAM和仅有20％的CLB资源的设计可能不是“拥挤”设计。
如果使用80％的CLB资源，则可能难以保持接近Block RAM的最大工作频率的工作时钟频率。
您设计的预期时钟频率是多少？
不要忽略CLB之间以及CLB和BRAM之间的互连延迟。
您在高带宽系统设计方面的经验如何，尤其是数据通路和流水线？
如果您有兴趣接近所选设备的工作频率限制，您的技能和才能将影响您的结果。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Your question is broad and vague, and here is the appropriate broad and vague answer:
Everything in your design may affect the operating frequency of your design, including the BRAMs.
You
can implement a design which uses 90% of the devices's available Block RAM while maintaining the full bandwidth (operating clock frequency) of the Block RAMs. If you are reasonably careful, this should not be difficult to achieve. This depends heavily on the rest of your design.
A design which uses 90% of the on-chip Block RAM and only 20% of the CLB resources is probably NOT a 'congested' design. If 80% of the CLB resources are utilised, you might have considerable difficulty maintaining an operating clock frequency which approaches the max operating frequency of the Block RAM.
What is the expected clock frequency for your design? Don't overlook the interconnect delays between CLBs, and between CLBs and BRAMs.
How experienced are you in high-bandwidth system design, especially datapaths and pipelines? Your skills and talents will affect your outcome, if you are interested in approaching the operating frequency limits of your selected device.
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post
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