使用DCM怎么生成vhdl文件

yuanran写道：您好！
我是FPGA设计的新手。
我想在我的项目中使用DCM，但是，在我执行Xilinx时钟向导之后，没有生成响应的vhdl文件。
我想知道我该怎么生成这个vhdl文件。
我还有其他步骤吗？
谢谢你的考虑！ 
不要使用时钟向导。
从库中实例化DCM和支持缓冲区。
你是新手，所以越早学会不依赖任何Xilinx提供的IP或“向导”，就越好。
----------------------------是的，我这样做是为了谋生。



以下为原文

yuanran wrote:
Hello!I am sort of new to FPGA Design. I want to use DCM in my project, however,after I do after Xilinx Clocking Wizard, there is no responding vhdl file generated. I want to know what should I to generate this vhdl file. Is there any other steps I do not do yet? thank you for your consideraion!
 
 

Don't use the clocking wizard. Instantiate the DCM and the supporting buffers from the library. You're new, so the sooner you learn to not rely on any Xilinx-provided IP or "Wizard," the better.
----------------------------Yes, I do this for a living.

检查项目设置以查看是否启用HDL输出以及设置输出目录的位置。
我最近遇到类似的问题，当我开始coregen，打开一个以前保存的项目，生成一个新的核心，关闭coregen然后找不到输出。
我打开的项目已将输出目录设置为我不在的那个，在我更改到正确的目录后，新的输出文件是正确的，我告诉coregen放置它们。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Check your project settings to see if you enable the HDL output as well as where you set the output directory.
 
I came across a similar issue recently when I started coregen, opened a previously saved project, generated a new core, closed coregen and then couldn't find the output.  The project that I opened had set the output directory set to one that I wasn't in and after I changed to the correct directory the new output files were right were they where I told coregen to put them.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

谢谢你，先生！
我已经解决了这些问题。
但我不知道为什么。
我唯一要做的就是删除所有文件并重新添加它们。
然后一切都很好。
疯！
哈哈



以下为原文

Thank you,Sir!
I have solved the problems. But I do not know why. the only thing I do is to remove all the file and add them again. then everything goes fine.
 Crazy!
haha