无法使用硬件评估许可证生成比特流

@pgrangeray
使用该信息从以下答复记录中获取生成的IP中的许可证信息，并查看生成的IP是否实际选择了HW Eval许可证。
https://www.xilinx.com/support/answers/44033.html
--Syed
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以下为原文

@pgrangeray
 
Use the information to get the License info from the generated IP from the following Answer record and see if your generated IP is actually picking HW Eval license. 
https://www.xilinx.com/support/answers/44033.html
 
--Syed
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@syedz
所以，我得到：
Proj_IP = v_cresample_0 license key = v_cresample@2013.03



以下为原文

@syedz
 
So, i get : 
 
Proj_IP = v_cresample_0 license key = v_cresample@2013.03

@pgrangeray
这提供了很多信息。
您可以运行以下TCL命令并在USED_LICENSE_KEYS下共享信息吗？
report_property -all [get_ips v_cresample *]
如果它具有“design_linking”，则表示该工具在生成期间未选择此IP的HW Eval许可证。
如果重置输出产品后跟生成输出仍然给出相同的行为，那么我怀疑问题必须与您的许可证文件有关（它是否已过期或您在生成许可证文件时使用了错误的HostID）
你能共享HW Eval许可文件（.lic）和xinfo.txt文件吗？
从Vivado TCL控制台运行以下命令以生成xinfo.txt。
report_environment -file xinfo.txt
运行该命令后，只需键入“pwd”，这将显示生成xinfo.txt文件的路径。
您可以浏览到该路径并找到该文件。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@pgrangeray
 
This doesn't give much info. Can you run the below TCL command and share the information under USED_LICENSE_KEYS?
report_property -all [get_ips v_cresample*]
 
If it has "design_linking" then it means that tool did not pick the HW Eval license for this IP during generation. 
If reset output products followed by generate outputs is still giving the same behaviour then I suspect the issue must be with your license file (either it got expired or you have used incorrect HostID when generating license file)
 
Can you share the HW Eval license file (.lic) and xinfo.txt file?  Run the following command from Vivado TCL console to generate xinfo.txt.
report_environment -file xinfo.txt
 
After running the command just type “pwd” this will show you the path where the xinfo.txt file is generated. You can browse to that path and find the file.    
 
--Syed
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@syedz
输出命令：
report_property -all [get_ips v_cresample *]警告：[Vivado 12-3670]只应在表示此IP的文件对象上查询generate_synth_checkpoint属性。
使用get_files命令访问文件对象。警告：[Vivado 12-3672]只应在表示此IP的文件对象上查询is_managed属性。
使用get_files命令访问文件对象。属性类型只读ValueALLOWED_SIM_TYPES string * true rtlBOARD string trueCLASS string true ipCONFIG.ACLK_INTF.FREQ_HZ string false 148500000CONFIG.Component_Name string false v_cresample_0CONFIG.S_AXI_ACLK_INTF.FREQ_HZ string false 100000000CONFIG.active_cols string false 1920CONFIG.active_rows
string false 1080CONFIG.chroma_parity string false oddCONFIG.convert_type string false 1CONFIG.field_parity string false oddCONFIG.has_axi4_lite string false falseCONFIG.has_debug string false falseCONFIG.has_intc_if string false falseCONFIG.interlaced string false falseCONFIG.m_axis_video_format string false 3CONFIG.max_cols string false 1920CONFIG.num_h_taps
string false 2CONFIG.num_v_taps string false 0CONFIG.s_axis_video_data_width string false 8CONFIG.s_axis_video_format string false 2CORE_REVISION int true 13DELIVERED_TARGETS string * true cmodel testbench changelog simulation synthesis instantiation_templateDESIGN_TOOL_CONTEXTS string
*真正的HDL IPI SysgenIPDEF串真xilinx.com:ip:v_cresample:4.0IP​​_CORE_CONTAINER串真正的C：/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/sources_1/ip/v_cresample_0.xcixIP_DIR串真正的C：/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/
sources_1 / IP / v_cresample_0IP_FILE串真正的C：/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/sources_1/ip/v_cresample_0/v_cresample_0.xciIS_LOCKED布尔真0KNOWN_TARGETS串*真正cmodel测试平台的changelog模拟合成instantiation_templateNAME串真v_cresample_0PART串真xc7a50tfgg484-2REQUIRES_VIP布尔trueSCOPE串
trueSELECTED_SIM_MODEL string false rtlSTALE_TARGETS string * trueSUPPORTED_TARGETS string * true cmodel testbench changelog simulation synthesis instantiation_templateSUPPORTS_MODREF bool true 1SW_VERSION string true 2018.1UNSUPPORTED_SIMULATORS string * trueUPGRADE_RESULT
string trueUPGRADE_VERSIONS string * trueUSED_LICENSE_KEYS string * true {{cmodel {v_cresample@2013.03 hardware_evaluation}} {testbench {v_cresample@2013.03 hardware_evaluation}} {changelog {v_cresample@2013.03 hardware_evaluation}} {simulation {v_cresample@2013.03 hardware_evaluation}} {synthesis {v_cresample @
2013.03 hardware_evaluation}} {instantiation_template {v_cresample@2013.03 hardware_evaluation}}} USER_LOCKED bool false 0
许可证文件位于.zip中。
xinfo.txt 74 KB
Xilinx.zip 1 KB



以下为原文

@syedz
 
Output of the command : 
 
report_property -all [get_ips v_cresample*]
WARNING: [Vivado 12-3670] The generate_synth_checkpoint property should only be queried on the file object representing this IP. Use the get_files command to access file objects.
WARNING: [Vivado 12-3672] The is_managed property should only be queried on the file object representing this IP. Use the get_files command to access file objects.
Property Type Read-only Value
ALLOWED_SIM_TYPES string* true rtl
BOARD string true
CLASS string true ip
CONFIG.ACLK_INTF.FREQ_HZ string false 148500000
CONFIG.Component_Name string false v_cresample_0
CONFIG.S_AXI_ACLK_INTF.FREQ_HZ string false 100000000
CONFIG.active_cols string false 1920
CONFIG.active_rows string false 1080
CONFIG.chroma_parity string false odd
CONFIG.convert_type string false 1
CONFIG.field_parity string false odd
CONFIG.has_axi4_lite string false false
CONFIG.has_debug string false false
CONFIG.has_intc_if string false false
CONFIG.interlaced string false false
CONFIG.m_axis_video_format string false 3
CONFIG.max_cols string false 1920
CONFIG.num_h_taps string false 2
CONFIG.num_v_taps string false 0
CONFIG.s_axis_video_data_width string false 8
CONFIG.s_axis_video_format string false 2
CORE_REVISION int true 13
DELIVERED_TARGETS string* true cmodel testbench changelog simulation synthesis instantiation_template
DESIGN_TOOL_CONTEXTS string* true HDL IPI Sysgen
IPDEF string true xilinx.com:ip:v_cresample:4.0
IP_CORE_CONTAINER string true c:/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/sources_1/ip/v_cresample_0.xcix
IP_DIR string true c:/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/sources_1/ip/v_cresample_0
IP_FILE string true c:/Projet_Vivado/project_Optsys_NB_50fps_multilayer/project_Optsys_NB_50fps_multilayer.srcs/sources_1/ip/v_cresample_0/v_cresample_0.xci
IS_LOCKED bool true 0
KNOWN_TARGETS string* true cmodel testbench changelog simulation synthesis instantiation_template
NAME string true v_cresample_0
PART string true xc7a50tfgg484-2
REQUIRES_VIP bool true
SCOPE string true
SELECTED_SIM_MODEL string false rtl
STALE_TARGETS string* true
SUPPORTED_TARGETS string* true cmodel testbench changelog simulation synthesis instantiation_template
SUPPORTS_MODREF bool true 1
SW_VERSION string true 2018.1
UNSUPPORTED_SIMULATORS string* true
UPGRADE_RESULT string true
UPGRADE_VERSIONS string* true
USED_LICENSE_KEYS string* true {{cmodel {v_cresample@2013.03 hardware_evaluation}} {testbench {v_cresample@2013.03 hardware_evaluation}} {changelog {v_cresample@2013.03 hardware_evaluation}} {simulation {v_cresample@2013.03 hardware_evaluation}} {synthesis {v_cresample@2013.03 hardware_evaluation}} {instantiation_template {v_cresample@2013.03 hardware_evaluation}}}
USER_LOCKED bool false 0
 
Licence file is in the .zip.
            xinfo.txt ‏74 KB                Xilinx.zip ‏1 KB