STA警告，如果打开项目的TimeN.HTML，您将发现项目中列出的安装路径/违规行为。如果单击它们，您可以看到完整路径、由每个路径贡献的延迟和松弛。
如果松弛是负的，则不能在集合FRQ上操作总线CLK，min将是67 MHz，以避免任何STA警告和问题。
之所以存在STA警告是因为在UART组件的输入引脚中设置了双同步选项，如果使它们透明，则不再有STA约束。
这是因为，在PIN级的同步与总线时钟和UART路径中的延迟不能满足该定时。
因此，您可以减少总线CLK或将输入UART引脚更改为透明模式（双击PIN & GT；PIN & GT；输入-GT；同步模式）。
后者不应该有任何问题。
如果你担心噪音，使用好的过采样和3个轮询方法中的2个。
以上来自于百度翻译
以下为原文
STA warnings , if you open the timing.html of your project you will find the Setup path /violations listed in the project .If you click on them you can see the complete path ,delay contributed by each path and the slack.
if the the slack is negative , you cannot operate the Bus Clk at the set freq, min would be 67 MHz to avoid any STA warnings and issues.
The reason there are STA warnings are because of the Double sync option set in the input pins to the UART component, if you make them transparent, you do not have STA contraints any more.
This is because ,the Synchronization at the pin level is with BUS clock and the delay in UART path cannot meet this timing.
So you can either reduce the BUS clk or change the input UART pins to transparent mode(Double click pin-->Pins-->Input-->Sync mode).
The latter should not have any issues.
If you are concerned about noise ,use good oversampling and 2 out of 3 polling methods.
STA警告，如果打开项目的TimeN.HTML，您将发现项目中列出的安装路径/违规行为。如果单击它们，您可以看到完整路径、由每个路径贡献的延迟和松弛。
如果松弛是负的，则不能在集合FRQ上操作总线CLK，min将是67 MHz，以避免任何STA警告和问题。
之所以存在STA警告是因为在UART组件的输入引脚中设置了双同步选项，如果使它们透明，则不再有STA约束。
这是因为，在PIN级的同步与总线时钟和UART路径中的延迟不能满足该定时。
因此，您可以减少总线CLK或将输入UART引脚更改为透明模式（双击PIN & GT；PIN & GT；输入-GT；同步模式）。
后者不应该有任何问题。
如果你担心噪音，使用好的过采样和3个轮询方法中的2个。
以上来自于百度翻译
以下为原文
STA warnings , if you open the timing.html of your project you will find the Setup path /violations listed in the project .If you click on them you can see the complete path ,delay contributed by each path and the slack.
if the the slack is negative , you cannot operate the Bus Clk at the set freq, min would be 67 MHz to avoid any STA warnings and issues.
The reason there are STA warnings are because of the Double sync option set in the input pins to the UART component, if you make them transparent, you do not have STA contraints any more.
This is because ,the Synchronization at the pin level is with BUS clock and the delay in UART path cannot meet this timing.
So you can either reduce the BUS clk or change the input UART pins to transparent mode(Double click pin-->Pins-->Input-->Sync mode).
The latter should not have any issues.
If you are concerned about noise ,use good oversampling and 2 out of 3 polling methods.
举报
