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[问答]

微晶时钟输入不路由

我正试图在Virtex-5上放置一个非常简单的Microblaze（没有外设，只有一个时钟，复位和一个LED的单个GPIO）。
我使用位置F5作为我的时钟输入，但每次它到达Place＆amp;
路线，它出错了：
设计没有完全路由。
有1个信号没有
在这个设计中完全路由。
有关列表，请参阅“Microblaze1_top.unroutes”文件
所有未经发布的信号。
检查PAR报告中可能包含的其他警告
说明为什么这些网是无法清除的。
这些网也可以评估
在FPGA编辑器中，通过在列表窗口中选择“未布线的网络”。
在unroutes文件中，它只是说：
警告：ParHelpers：360  - 设计未完全路由。
fpga_0_clk_1_sys_clk_pin_IBUF
关于为什么会发生这种情况或如何解决它的任何想法？

以上来自于谷歌翻译


以下为原文

I'm trying to put an extremely simple Microblaze on a Virtex-5 (no peripherals, just a clock, reset, and single GPIO for an LED).  I'm using location F5 for my clock input, but every time it gets to Place & Route, it errors out with:

Design is not completely routed. There are 1 signals that are not   completely routed in this design. See the "Microblaze1_top.unroutes" file for a list of   all unrouted signals. Check for other warnings in your PAR report that might   indicate why these nets are unroutable. These nets can also be evaluated   in FPGA Editor by selecting "Unrouted Nets" in the List Window. And inside the unroutes file, it just says:
WARNING:ParHelpers:360 - Design is not completely routed.   fpga_0_clk_1_sys_clk_pin_IBUF Any ideas as to why this is happening or how to solve it?

回帖（10）

何培芬

2018-10-12 14:41:57
感谢您的帮助;
你肯定让我走上了正确的道路。
我尝试使用从输入引脚到微灯时钟输入的IBUFG，但仍然说它无法路由。
然而，我能够通过首先将输入引脚发送到IBUF，然后从那里发送到BUFG，最后发送到微型发光器来使其工作。
再次感谢。
在原帖中查看解决方案

以上来自于谷歌翻译


以下为原文

Thank you for your help; you definitely set me on the right path.
 
I tried using an IBUFG from the input pin to the microblaze clock input, but that still said it was unable to route.
 
However, I was able to get it to work by first sending the input pin to an IBUF, and then from there to a BUFG, and finally to the microblaze.
 
Thanks again.
View solution in original post
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李刚

2018-10-12 14:49:33
我猜想F5不是您正在使用的零件和包的时钟输入的有效位置。
但是由于你还没有发布这些细节，所以无法确定。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“

以上来自于谷歌翻译


以下为原文

I would guess that F5 is not a valid location for a clock input for the part and package that you are using. But as you have not posted those details, it is impossible to be sure.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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何培芬

2018-10-12 15:04:57
谢谢，但遗憾的是F5是一个用户IO引脚，只需使用Verilog即可作为时钟输入工作。
但是通过将其作为Microblaze的时钟输入，它表示它无法路由它。我是新手，所以如果有更多信息我应该提供以帮助隔离问题，请告诉我。

以上来自于谷歌翻译


以下为原文

Thank you, but unfortunately F5 is a user IO pin that works fine as a clock input when just using Verilog.  But by making it the clock input for a Microblaze, it says that it is not able to route it.

I am new to this, so please let me know if there is more information I should provide to help isolate the problem.
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黄淳

2018-10-12 15:13:37
kdc71726写道：谢谢，但不幸的是F5是一个用户IO引脚，只使用Verilog作为时钟输入工作正常。
但是通过将其作为Microblaze的时钟输入，它表示它无法路由它。我是新手，所以如果有更多信息我应该提供以帮助隔离问题，请告诉我。
什么是确切的错误消息？
----------------------------是的，我这样做是为了谋生。

以上来自于谷歌翻译


以下为原文

kdc71726 wrote:
Thank you, but unfortunately F5 is a user IO pin that works fine as a clock input when just using Verilog. But by making it the clock input for a Microblaze, it says that it is not able to route it.

I am new to this, so please let me know if there is more information I should provide to help isolate the problem.
What's the exact error message?
----------------------------Yes, I do this for a living.
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