ucf中如果没有引脚约束，时序仿真的结果会受到影响吗？

您可以信任时序分析。
不同的IO位置具有不同的时序结果。
问候，brucey -----------------------------------------------
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以下为原文

You can trust timing analysis. Different IO locations has different timing results.Regards,
brucey
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哦，如果这样，也就是说，没有布局引脚，时序仿真的结果仍然是信任或正确的。
我能理解ISE将是布局自动引脚吗？
如果布局自动引脚，它的原理是什么？
你能粗略地给我描述一下吗？非常感谢你！



以下为原文

oh, if this, that is to say ,without layout pins,the result of timing simulation  is still trust or correct. Can I understand that ISE will be layout automatical pins? if  layout automatic pins,what it is the principle? can you give me describle roughly ?
Thank you very much!

我对这个原则不太清楚。
但是，工具会尝试查找有效位置。
问候，brucey -----------------------------------------------
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如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .--------------------
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以下为原文

I am not quite clear about the priciple. However, tool tries to find valid locations.
Regards,
brucey
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如果PCB尚未布局，并且您打算将电路板设计为与自动FPGA布局相对应，则放置和时序结果有效。
通常首先设计电路板，然后您非常需要对所有IO进行位置约束。



以下为原文

The placement and timing results are valid if the PCB hasn't been layed out yet and you intend to design the board to correspond to the automatic FPGA placement. Often the board is designed first and then you have a very serious need for for location constraints on all IO.