N，
您的设计对时序有一些限制，可能只是一个简单的周期约束。
在硬件中，信号必须在时钟（设置）之前到达目的地并且在时钟之后持续（保持）。
每个连接都需要一个有限的时间来传播信号：路径太长（有太多的段）还是满足时序约束？
设计选择基于固定资源的放置，它不能移动，例如您希望使用的IO引脚。
然后它必须路由所有布线以满足周期约束。
它不能满足约束，它必须撕裂，移动，重新路由，并再试一次。
此过程可能会失败：您可能会将约束条件设置得太紧（如果没有更快的速度等级部件就无法满足，或者使用管道阶段修改设计等）。
这些工具也可能过于愚蠢，无法通过手动干预找到最佳路由和放置（请参阅下面的PlanAhead）。
消息显示您的进度。
如果删除任何.ucf（约束）并让工具选择IO引脚，只是放置和布线设计，忽略时序，它将运行得非常快。
设计越受限制，找到满足所有约束的布局和布线所需的时间就越长。
PlanAhead用于那些真正想要更快地满足其约束条件的人，以预先规划主要元素和IO引脚的位置。
将逻辑上的东西放在接近他们将要使用的东西上是有意义的，并且只有人类才能做到（HDL代码不告诉工具如何满足时序，只有设计工程师能够洞察这个问题
）。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
n,
Your design has some constraints for timing, probably just a simple period constraint. In hardware, signals have to get to their destination ahead of the clock (setup) and last after the clock (hold). Each connection takes a finite time to propagate the signal: is the path too long (has too many segments) or does it meet the timing constraints?
The design chooses a placement based on fixed resources which it can not move, such as what IO pins you wish to use. Then it has to route all the wiring to meet the period constraint. It is can not meet the constraint, it has to rip up, move things, reroute, and try again.
This process may fail: you may have the constraints too tight (can not be met without going to a faster speed grade part, or modifying your design by using pipeline stages, etc.).
It is also possible that the tools are just too stupid to find the optimal routing and placement without some manual intervention (see PlanAhead, below).
The messages show your progress.
If you remove any .ucf (constraints) and let the tools pick the IO pins, and just place and route the design, ignoring timing, it will run very fast.
The more constrained the design, the longer it will take to find a placement and routing that meets all constraints.
PlanAhead is used by those who really want to meet their constraints much more quickly to pre-plan the placement of major elements, and IO pins. Placing things logically close to what they are going to use just makes sense, and is something that only human beings seem able to do (the HDL code doesn't tell the tool how to meet timing, only the design engineer has insight into that problem).
Austin Lesea
Principal Engineer
Xilinx San Jose
N，
您的设计对时序有一些限制，可能只是一个简单的周期约束。
在硬件中，信号必须在时钟（设置）之前到达目的地并且在时钟之后持续（保持）。
每个连接都需要一个有限的时间来传播信号：路径太长（有太多的段）还是满足时序约束？
设计选择基于固定资源的放置，它不能移动，例如您希望使用的IO引脚。
然后它必须路由所有布线以满足周期约束。
它不能满足约束，它必须撕裂，移动，重新路由，并再试一次。
此过程可能会失败：您可能会将约束条件设置得太紧（如果没有更快的速度等级部件就无法满足，或者使用管道阶段修改设计等）。
这些工具也可能过于愚蠢，无法通过手动干预找到最佳路由和放置（请参阅下面的PlanAhead）。
消息显示您的进度。
如果删除任何.ucf（约束）并让工具选择IO引脚，只是放置和布线设计，忽略时序，它将运行得非常快。
设计越受限制，找到满足所有约束的布局和布线所需的时间就越长。
PlanAhead用于那些真正想要更快地满足其约束条件的人，以预先规划主要元素和IO引脚的位置。
将逻辑上的东西放在接近他们将要使用的东西上是有意义的，并且只有人类才能做到（HDL代码不告诉工具如何满足时序，只有设计工程师能够洞察这个问题
）。
Austin Lesea主要工程师Xilinx San Jose
以上来自于谷歌翻译
以下为原文
n,
Your design has some constraints for timing, probably just a simple period constraint. In hardware, signals have to get to their destination ahead of the clock (setup) and last after the clock (hold). Each connection takes a finite time to propagate the signal: is the path too long (has too many segments) or does it meet the timing constraints?
The design chooses a placement based on fixed resources which it can not move, such as what IO pins you wish to use. Then it has to route all the wiring to meet the period constraint. It is can not meet the constraint, it has to rip up, move things, reroute, and try again.
This process may fail: you may have the constraints too tight (can not be met without going to a faster speed grade part, or modifying your design by using pipeline stages, etc.).
It is also possible that the tools are just too stupid to find the optimal routing and placement without some manual intervention (see PlanAhead, below).
The messages show your progress.
If you remove any .ucf (constraints) and let the tools pick the IO pins, and just place and route the design, ignoring timing, it will run very fast.
The more constrained the design, the longer it will take to find a placement and routing that meets all constraints.
PlanAhead is used by those who really want to meet their constraints much more quickly to pre-plan the placement of major elements, and IO pins. Placing things logically close to what they are going to use just makes sense, and is something that only human beings seem able to do (the HDL code doesn't tell the tool how to meet timing, only the design engineer has insight into that problem).
Austin Lesea
Principal Engineer
Xilinx San Jose
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