CY7C2665KV18终端阻抗和上拉电阻

你好，
我们使用一个QDR存储器（CY7C2665 KV18，时钟频率为1.8V，1.5MHz为HSTL逻辑），在这个数据表（1）HTTP://wwwyCysCy.COM/FIL/5638 6/下载和这些准则[ 1 ] HTTP://wwwyCysP.COM/FIL/35596/下载。
QDR存储器连接到MPF300 TS-1 FCG1152I/EES FPGA器件。在我们项目的当前状态中，我们已经路由了所有长度、阻抗（50欧姆）匹配的数据总线、地址和控制信号，
但是最近，我们注意到，在找到这个论坛足够的时间之后（1）HTTPS://Cultuy.CyPr.com／thRead /27 706之后，我们可能误解了阻抗配置（2）和（2）。开始＝0和tTSt= 0
在第2页（信号完整性和布局指南）中，应用笔记指出：
“CyPress软件包被路由以获得所有的痕迹。
50±10%。所有的轨迹必须被路由到50 -π。
阻抗，应该没有阻抗
不连续性。”
好的，做完了。
“考虑使用串联电阻匹配总驱动器
侧阻抗为50Ω。
好的，如果我们的输出驱动器阻抗小于50欧姆，这是正确的，所以我们决定将RQ电阻设置为250欧姆。然后在第24页〔2〕第七段，我们有：
“终端电阻（R）的值为50Ω。
因为大多数设计都具有跟踪特性。
阻抗50℃。终端电阻值
必须等于特性阻抗
痕迹。”
考虑到〔3〕，如果低范围设置ODT但输出缓冲器为35欧姆，RQ等于175（接近50欧姆）。一旦我们的轨道被路由，这个解决方案对于我们来说太难实现了，在2中同样保留了第八段。
但是在[ 2 ]的第九段中，应用程序说：
“另一个建议是保持RQ等于。
（250）存储器的输出驱动器阻抗为
50Ω和ODT引脚低，存储器的ODT值
75℃。在这种情况下，反射系数是
有50Ω和客户的阻抗
不需要使用外部电阻来匹配阻抗。
我们可以推断出，ODT输入为75欧姆，这对信号完整性没有显著影响吗？在这点上有些困惑。
在图2的第23页后面的图39中，这是否意味着我们必须在WPS/RPS控制信号、CP/CPYN和地址总线上设置强制终端电阻，因为没有ODT信号？
如果我们没有损失什么，在这一点上，我们认为克服我们在布局影响最小的问题可能的解决方案：
设置RQ＝250欧姆
设置ODT pin Low，所以ODT信号在75欧姆。
如果地址和其他的ODT信号必须有上拉电阻（50欧姆）到VTT终止，终止使用VTT稳压器（例如ncp51400 http://www.onsemi.com/pub/collateral/ncp51400-d.pdf或另一个），然后把0201个50欧姆的电阻接近Fanout vias。
这个解决方案能有效吗？否则还有什么选择？
提前感谢

以上来自于百度翻译

   以下为原文
  Hello,

We are using a QDR memory (CY7C2665KV18 clocked at 450 MHz with 1.8V core and 1.5V for HSTL logic)  following this datasheet [1] http://www.cypress.com/file/45386/download and these guidelines [1] http://www.cypress.com/file/38596/download.
The QDR memory is connected to a MPF300TS-1FCG1152I/EES FPGA device.  In the current state of our project we have routed all data buses, address and control signals matched in length and impedance (50 Ohm),
but recently, we have noticed that we could have misunderstood impedance configuration following [1] and [2] after having found this forum enough time later [3] https://community.cypress.com/thread/27706?start=0&tstart=0

In [2] at page 11 (Signal integrity and Layout Guidelines), the app note says:

"Cypress Packages are routed to obtain all traces to
50 Ω ± 10%. All traces must be routed to have 50-Ω
impedance and should have no impedance

discontinuities."

Ok, done.

"Consider using a series resistor to match total driver
side impedance to 50 Ω."

Ok, this is true if our output driver impedance is less to 50 Ohm, so we decided set the RQ resistor to 250 Ohm. Then at page 24 in [2] 7th paragraph we have:

"The value of the termination resistor (R) is 50 Ω
because most designs have a trace characteristic
impedance of 50 Ω. The termination resistor value
must be equal to the characteristic impedance of the

trace."

Considering [3], this is true (close to 50 Ohm) for RQ equal to 175 if Low range setting ODT but output buffers are to 35 Ohm. Once our tracks are routed this solution is too hard to implement for us at this moment, the same remains for 8th paragraph in [2].
But in the 9th Paragraph of [2], the app says:

"The other recommendation is to keep RQ equals to
250 Ω then the output driver impedance of memory is
50 Ω and with ODT pin low, the ODT value of memory
is 75 Ω. In this case, the reflection co-efficient is
positive with trace impedance of 50 Ω and customer
does not need to use external resistors to match the impedance. "

Can we infer here that the ODT inputs are at 75 Ohm and this does not have remarkable effect in signal integrity? were somewhat confused at these points.
Following figure 39 at page 23 of [2], does this implies that we have to put mandatory termination resistors at WPS/RPS control signals, CP/CP_N, and address bus because there aren't ODT signals?

If we didn't loss anything at this point, we have thought a possible solution to overcome our problem with minimal impact in layout:

Set RQ = 250 Ohm
Set ODT pin Low, so ODT signals at 75 Ohm.
if Address and other ODT signals must be terminated with a pull up resistor (50 Ohm) to VTT, use a VTT termination regulator (for example NCP51400 http://www.onsemi.com/pub/Collateral/NCP51400-D.PDF or another one), and then place 0201 50 Ohm resistors close to Fanout vias.

can be this solution effective? otherwise what are the alternatives?

Thanks in advance

回帖（1）

徐晨曦

2018-9-11 15:06:13

嗨，劳尔，
请在下面找到我的评论
Q1）我们可以推断出，ODT输入为75欧姆，这对信号完整性没有显著影响吗？
是的。
Q2）在图39的第2页第23页，这是否意味着我们必须在WPS/RPS控制信号CP/CPYN和地址总线上设置强制终端电阻，因为没有ODT信号？
是的，你的理解是正确的。
Q3）如果我们在这一点上没有损失任何东西，我们已经想到了一个可能的解决方案来克服我们的问题，在布局上的影响最小：
设置RQ＝250欧姆
设置ODT pin Low，所以ODT信号在75欧姆。
如果地址和其他ODT信号必须用一个上拉电阻（50欧姆）终止到VTT，使用VTT终端调节器（例如NCP51400 HTTP://www. OnMy.COM/PUB/PrAUTALAL/NCP51400 D.PDF或另一个），然后将0201个50欧姆电阻器靠近Fanout vias。
这个解决方案能有效吗？否则还有什么选择？
这个解决方案会好的。
谢谢和问候，
普拉迪普塔

以上来自于百度翻译

以下为原文
Hi Raul,

Please find my comments below

Q1) Can we infer here that the ODT inputs are at 75 Ohm and this does not have remarkable effect in signal integrity?
Ans) Yes.

Q2) Following figure 39 at page 23 of [2], does this implies that we have to put mandatory termination resistors at WPS/RPS control signals, CP/CP_N, and address bus because there aren't ODT signals?
Ans) Yes, your understanding is correct.

Q3) If we didn't loss anything at this point, we have thought a possible solution to overcome our problem with minimal impact in layout:
Set RQ = 250 Ohm
Set ODT pin Low, so ODT signals at 75 Ohm.
if Address and other ODT signals must be terminated with a pull up resistor (50 Ohm) to VTT, use a VTT termination regulator (for example NCP51400 http://www.onsemi.com/pub/Collateral/NCP51400-D.PDF or another one), and then place 0201 50 Ohm resistors close to Fanout vias.
can be this solution effective? otherwise what are the alternatives?
Ans) This solution will be okay.

Thanks and Regards,
Pradipta.

更多回帖

李琴

CY7C2665KV18终端阻抗和上拉电阻

回帖（1）

徐晨曦

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