ATC2核心是一个坚定的核心。
使用Core Inserter创建和插入核心时，核心不会影响设计的合成。
在设计中包含ATC2内核可能会影响整个FPGA设计的布局和布线。
在典型的应用中，效果应该很小。
对设计时序的影响将取决于核心的配置方式（例如，您选择的每个存储区的信号数量和存储区总数）以及所使用的特定FPGA器件上可用的资源数量。
状态核心：ATC2状态核心包括一个记录数据的触发器。
ATC2内核在每个被探测的信号上增加一个额外的负载（翻转）。
此负载将被考虑到路由中以满足用户指定的时序约束。
这种翻转有助于工具满足大多数类型设计的时序约束。
定时内核：ATC2定时内核为每个被探测的信号增加了线路负载。
该线负载是在设计的布局和布线期间被忽略的错误路径。
因此，定时内核对设计时序的影响微乎其微。
您可以通过查看设计工具生成的延迟文件来确定信号之间的偏差，以估计这种差异。一旦ATC2内核（状态或定时内核）处于设计中，从信号库切换到信号库不会改变设计时序
，因为已经建立了所有连接。
以上来自于谷歌翻译
以下为原文
The ATC2 core is a firm core. The core will not affect the synthesis of the design when you create and insert the core using Core Inserter. The inclusion of an ATC2 core in the design may affect the placement and routing of the overall FPGA design. In typical applications, the effect should be small. The effect on design timing will depend on how the core is configured (for example, the number of signals you choose per bank and the total number of banks) and the number of resources available on the particular FPGA device being used.
State core: The ATC2 state core includes a flop that registers data. The ATC2 core adds one additional load (flop) on each signal probed. This load will be factored into routing to meet user specified timing constraints. This flop helps the tools meet timing constraints for most types of designs.
Timing core: The ATC2 timing core adds a wire load for each signal probed. This wire load is a false path that is ignored during place and route of the design. Hence, the timing core has minimal-to-no effect on design timing. You can determine the skew between signals by viewing the delay file generated by the design tools to estimate this difference.
Once the ATC2 core (either state or timing core) is in the design, switching from signal bank to signal bank does not change design timing, as all connections have been already made.
ATC2核心是一个坚定的核心。
使用Core Inserter创建和插入核心时，核心不会影响设计的合成。
在设计中包含ATC2内核可能会影响整个FPGA设计的布局和布线。
在典型的应用中，效果应该很小。
对设计时序的影响将取决于核心的配置方式（例如，您选择的每个存储区的信号数量和存储区总数）以及所使用的特定FPGA器件上可用的资源数量。
状态核心：ATC2状态核心包括一个记录数据的触发器。
ATC2内核在每个被探测的信号上增加一个额外的负载（翻转）。
此负载将被考虑到路由中以满足用户指定的时序约束。
这种翻转有助于工具满足大多数类型设计的时序约束。
定时内核：ATC2定时内核为每个被探测的信号增加了线路负载。
该线负载是在设计的布局和布线期间被忽略的错误路径。
因此，定时内核对设计时序的影响微乎其微。
您可以通过查看设计工具生成的延迟文件来确定信号之间的偏差，以估计这种差异。一旦ATC2内核（状态或定时内核）处于设计中，从信号库切换到信号库不会改变设计时序
，因为已经建立了所有连接。
以上来自于谷歌翻译
以下为原文
The ATC2 core is a firm core. The core will not affect the synthesis of the design when you create and insert the core using Core Inserter. The inclusion of an ATC2 core in the design may affect the placement and routing of the overall FPGA design. In typical applications, the effect should be small. The effect on design timing will depend on how the core is configured (for example, the number of signals you choose per bank and the total number of banks) and the number of resources available on the particular FPGA device being used.
State core: The ATC2 state core includes a flop that registers data. The ATC2 core adds one additional load (flop) on each signal probed. This load will be factored into routing to meet user specified timing constraints. This flop helps the tools meet timing constraints for most types of designs.
Timing core: The ATC2 timing core adds a wire load for each signal probed. This wire load is a false path that is ignored during place and route of the design. Hence, the timing core has minimal-to-no effect on design timing. You can determine the skew between signals by viewing the delay file generated by the design tools to estimate this difference.
Once the ATC2 core (either state or timing core) is in the design, switching from signal bank to signal bank does not change design timing, as all connections have been already made.
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