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在ISE 14.7的布局和布线阶段，我遇到了让我的设计通过的问题。
这是针对Virtex6，partxc6vlx760，封装ff1760，速度-2。 首先显示的布局布线期间的消息是这样的。 警告：路由：436 - 路由器检测到一个或多个连接的不可路由情况。 路由器将完成设计的其余部分并将其保留为未布线状态。 导致此行为的原因是放置问题或不可路由的放置约束。为了允许您使用FPGA编辑器来隔离问题，以下是（最多10个）此类不可路由连接的列表：Unroutable信号：emul_v6_iserdes_fpga4_fpga2_s0_inst / is_clk_fast 销：emul_v6_iserdes_fpga4_fpga2_s0_inst / GEN_LANES [30] .emul_v6_iserdes_lane_inst / ISERDESE1_inst_master / CLK 消息中列出了更多信号，但为了简洁起见，将其删除。设计稍后在bitgen中失败，并显示错误消息，表示网络未完全路由。 我已经尝试使用非定时驱动选项和不同的约束来运行map和P＆amp; R以尝试获取它的路线并且它仍然失败。 我已经在fpga编辑器中查看了未布线的设计，看起来（至少对我而言）由于不同的GEN_LANES实例的放置分散开来，路由器无法连接它们。 我不确定这是否是实际问题，以及我应该如何解决它。 我有另一个fpga具有相同的模块“emul_v6_iserdes_fpga4_fpga2_s0_inst”，它完全没有P＆amp; R。 唯一的区别是serdes模块中实例化的通道数。 由于在fpga2和fpga4之间传递了大量信号，因此在这种情况下，它会导致我们的serdes创建大量通道。 大量的通道导致不同的实例相隔很远，导致路由问题？ 由于P＆amp; R.ncd太大，我附上了我的后贴图.ncd。 map.7z 15276 KB 以上来自于谷歌翻译 以下为原文 I have been having an issue getting my design to pass during the place and route phase of ISE 14.7. This is targetting a Virtex6, part xc6vlx760, package ff1760, speed -2. The message during Place and route that first shows up is this. WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: emul_v6_iserdes_fpga4_fpga2_s0_inst/is_clk_fast pin: emul_v6_iserdes_fpga4_fpga2_s0_inst/GEN_LANES[30].emul_v6_iserdes_lane_inst/ISERDESE1_inst_master/CLK There are a few more signals listed in the message, but removed for brevity. The design later fails in bitgen with an error message saying the net is not completely routed. I have tried running map and P&R with non-timing driven options and different constraints to try and get it route and it still fails. I have looked through the unrouted design in fpga editor and it seems (to me atleast) that because of the placement of different GEN_LANES instances, which are spread out far apart, the router has trouble connecting them. I am unsure if this is the actual problem and if it is how I should go about solving it. I have another fpga that has the same exact module "emul_v6_iserdes_fpga4_fpga2_s0_inst" and it passes P&R perfectly fine. The only difference is the number of lanes that is instantiated in the serdes module. Because of the large number of signals being passed between fpga2 and fpga4, it causes our serdes to create a large number of lanes in this case. And the large number of lanes causes different instances to be placed far apart, causing routing issues? I have attached my post-map .ncd as the P&R .ncd is too big. map.7z 15276 KB 
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从你的NCD文件中，BUFIO由MRCC IO驱动，这意味着BUFIO可以驱动上下的IO bank。
这是UG362的插图。 路由故障是由于某些ILOGIC负载超出BUFIO达到限制的事实。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 From you NCD file, the BUFIO is driven by MRCC IO, which means the BUFIO can drive into the IO bank above and below. Here's an illustration from UG362. The routing failure is due to the fact that some of the ILOGIC loads are beyond the BUFIO reaching limit. ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. -------------------------------------------------------------------------View solution in original post |
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这可能是结构性故障 - 需要连接在一起的两个组件之间没有路由（即，物理上不可能将一个输出路由到另一个的输入）。
您需要浏览连接列表并告诉我们每个组件是什么，或者发布此网络上所有连接的原理图。 如果涉及I / O，您需要告诉我们I / O所在的银行。 这显然是某种时钟连接 - 某些模块的时钟引脚的可用路径是有限的; 它们只是某些合法的时钟配置，你可能正在使用“其他东西”。 Avrum 以上来自于谷歌翻译 以下为原文 This is probably a structural failure - the two components that need to be connected together have no route between them (i.e. it is physically impossible to route the output of the one to the input of the other). You need to go through the list of connections and tell us what each component is, or post the schematic of all the connections on this net. If there are I/Os involved, you need to tell us which bank the I/O are are located in. This is clearly some kind of clock connection - the available routes to the clock pins of some modules are limited; they are only certain legal clocking configurations for them, and you are probably using "something else". Avrum |
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我附上了is_clk_fast信号路由的图片。
这是一个时钟信号。 我还附上了它所提供的组件的图片。 基本上它会进入Iserdes1_inst_master组件的“CLK和CLKB”输入引脚。 每个车道完成54次。 它由BUFIODQS驱动。 以上来自于谷歌翻译 以下为原文 I attached a picture of the routing of the is_clk_fast signal. It is a clock signal. I also attached a picture of the components it feeds into. Basically it goes into Iserdes1_inst_master component's "CLK and CLKB" input pins. This is done 54 times for each of the lanes. It is driven by the BUFIODQS. |
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从你的NCD文件中，BUFIO由MRCC IO驱动，这意味着BUFIO可以驱动上下的IO bank。
这是UG362的插图。 路由故障是由于某些ILOGIC负载超出BUFIO达到限制的事实。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 From you NCD file, the BUFIO is driven by MRCC IO, which means the BUFIO can drive into the IO bank above and below. Here's an illustration from UG362. The routing failure is due to the fact that some of the ILOGIC loads are beyond the BUFIO reaching limit. ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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谢谢，从BUFIO改为BUFR已经解决了这个问题。
以上来自于谷歌翻译 以下为原文 Thanks, changing from BUFIO to BUFR has fixed the issue. |
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