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【Artix-7 50T FPGA试用体验】（二）简单测试+解决问题

2016-10-29 15:05:43 3753

0 终于可以闲下来玩玩板子，写写总结了，最近天气都是阴雨连绵，很是潮湿。自从上次开箱以来，一直在忙，都没怎么动过板子了，上次遗留一个问题就是D10一直没亮，想来想去还是觉得应该是根本没有程序在跑，所以今天就来看看这个问题。解决D10灯的问题：先把下载下来的文档大体翻了翻，看到提供的例子7A50T_EthernetLite_LwIP_VIV2014_4中有好东西，就在7A50T_EthernetLite_LwIP_VIV2014_4demo文件夹下看到了批处理，查阅看了下里面有把已经存在的elf文件下载进去，所以直接点了demo_raw_apps.bat 果不其然下载完成，串口有了打印，D10也亮了。具体的执行信息如下： ====================================================================== Configuring FPGA **** Xilinx Microprocessor Debugger (XMD) Engine ** XMD v2014.4 SW Build 1071353 on Tue Nov 18 17:13:25 MST 2014 Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. Executing user script : download_bit.tcl Configuring Device 1 (xc7a50t) with Bitstream -- download.bit ...10..20...30..40..50...60..70..80...90..100Successfully downloaded bit file. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0362c093 6 xc7a50t Waiting 3 seconds to allow PHY negotiation to complete Loading memory filesystem and lwIP Raw Mode Applications **** Xilinx Microprocessor Debugger (XMD) Engine ** XMD v2014.4 SW Build 1071353 on Tue Nov 18 17:13:25 MST 2014 Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. XMD% JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0362c093 6 xc7a50t MicroBlaze Processor Configuration : ------------------------------------- Version............................9.4 Optimization.......................Performance Interconnect.......................AXI-LE MMU Type...........................No_MMU No of PC Breakpoints...............1 No of Read Addr/Data Watchpoints...0 No of Write Addr/Data Watchpoints..0 Instruction Cache Support..........on Instruction Cache Base Address.....0x80000000 Instruction Cache High Address.....0x8fffffff Data Cache Support.................on Data Cache Base Address............0x80000000 Data Cache High Address............0x8fffffff Exceptions Support................off FPU Support.......................off Hard Divider Support...............on Hard Multiplier Support............on - (Mul32) Barrel Shifter Support.............on MSR clr/set Instruction Support....on Compare Instruction Support........on Data Cache Write-back Support......on Fault Tolerance Support............off Stack Protection Support...........off Connected to "mb" target. id = 0 Starting GDB server for "mb" target (id = 0) at TCP port no 1234 System reset successfully Downloading Data File -- image.mfs at 0x84000000 Progress ....................................................................... ................................................................................ ................................................................................ .................................Done System Reset .... DONE Downloading Program -- lwip_raw_apps.elf section, .vectors.reset: 0x00000000-0x00000007 section, .vectors.sw_exception: 0x00000008-0x0000000f section, .vectors.interrupt: 0x00000010-0x00000017 section, .vectors.hw_exception: 0x00000020-0x00000027 section, .text: 0x80000000-0x8002615b section, .init: 0x8002615c-0x80026197 section, .fini: 0x80026198-0x800261b7 section, .ctors: 0x800261b8-0x800261bf section, .dtors: 0x800261c0-0x800261c7 section, .rodata: 0x800261c8-0x80028077 section, .data: 0x80028078-0x800286c7 section, .bss: 0x80028700-0x8023abdb section, .heap: 0x8023abdc-0x8025abdf section, .stack: 0x8025abe0-0x8027abdf Download Progress..10.20.30.40.50.60.70.80.90.Done Setting PC with Program Start Address 0x00000000 Processor started. Type "stop" to stop processor RUNNING> E:Artix-7 FPGA开发板资料7A50T7A50T_EthernetLite_LwIP_Vivado_2014_47A50T_Eth ernetLite_LwIP_VIV2014_4demo> 简单的测试了一下：网页可以正常的打开板子上的测试灯也正常的亮起来了：同时在串口也打印了http相关的信息：同时也用iperf简单的测试了一下网络的吞吐量（时长100s）： E:Artix-7 FPGA开发板资料7A50T7A50T_EthernetLite_LwIP_Vivado_2014_47A50T_Eth ernetLite_LwIP_VIV2014_4Iperf>cmd Microsoft Windows [版本版权所有 (c) 2009 Microsoft Corporation。保留所有权利。 E:Artix-7 FPGA开发板资料7A50T7A50T_EthernetLite_LwIP_Vivado_2014_47A50T_Eth ernetLite_LwIP_VIV2014_4Iperf>iperf.exe -c 192.168.8.103 -i 5 -t 100 ------------------------------------------------------------ Client connecting to 192.168.8.103, TCP port 5001 TCP window size: 8.00 KByte (default) ------------------------------------------------------------ [160] local 192.168.8.102 port 51715 connected with 192.168.8.103 port 5001 [ ID] Interval Transfer Bandwidth [160] 0.0- 5.0 sec 10.5 MBytes 17.6 Mbits/sec [160] 5.0-10.0 sec 10.2 MBytes 17.1 Mbits/sec [160] 10.0-15.0 sec 10.4 MBytes 17.5 Mbits/sec [160] 15.0-20.0 sec 10.9 MBytes 18.2 Mbits/sec [160] 20.0-25.0 sec 10.8 MBytes 18.2 Mbits/sec [160] 25.0-30.0 sec 11.0 MBytes 18.5 Mbits/sec [160] 30.0-35.0 sec 11.1 MBytes 18.7 Mbits/sec [160] 35.0-40.0 sec 10.9 MBytes 18.4 Mbits/sec [160] 40.0-45.0 sec 11.1 MBytes 18.5 Mbits/sec [160] 45.0-50.0 sec 9.70 MBytes 16.3 Mbits/sec [160] 50.0-55.0 sec 10.7 MBytes 18.0 Mbits/sec [160] 55.0-60.0 sec 11.4 MBytes 19.2 Mbits/sec [160] 60.0-65.0 sec 11.2 MBytes 18.9 Mbits/sec [160] 65.0-70.0 sec 10.2 MBytes 17.1 Mbits/sec [160] 70.0-75.0 sec 11.0 MBytes 18.4 Mbits/sec [160] 75.0-80.0 sec 11.2 MBytes 18.8 Mbits/sec [160] 80.0-85.0 sec 11.4 MBytes 19.0 Mbits/sec [160] 85.0-90.0 sec 10.1 MBytes 16.9 Mbits/sec [160] 90.0-95.0 sec 11.5 MBytes 19.2 Mbits/sec [160] 95.0-100.0 sec 11.3 MBytes 19.0 Mbits/sec [ ID] Interval Transfer Bandwidth [160] 0.0-100.0 sec 217 MBytes 18.2 Mbits/sec E:Artix-7 FPGA开发板资料7A50T7A50T_EthernetLite_LwIP_Vivado_2014_47A50T_Eth ernetLite_LwIP_VIV2014_4Iperf> 0
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