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【锆石A4 FPGA试用体验】VHDL状态机字符显示控制器的设计与调试

2016-10-26 10:21:40 3046 数据采集状态机

0 Vhdl语言严谨啊用状态机设计一个能使数码管显示多样字符的控制器： 1、用状态机控制3个数码管，按“000-StA-1bC-2FG-3HL- End”的顺序轮流显示以上字符，各组字符显示的时间间隔为1S，字符显示采用动态扫描方式实现。 2、设置2个外部操作开关，分别控制显示复位（复位到000状态）、显示暂停/继续功能。根据要求用visio或者在草稿子画出流程图这其中体现了自己的设计思想 Bdf为顶层为文件;当然顶层也可使用例化语句！ Vwf分析就不上了 --代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENtiTY SCAN_LED IS PORT ( CLK : IN STD_LOGIC; d0,d1,d2,d3,d4,d5,d6,d7:in STD_LOGIC_VECTOR(3 DOWNTO 0); SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出 BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); --位控制信号输出 END; ARCHITECTURE one OF SCAN_LED IS SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN P1:PROCESS( CNT8 ) BEGIN CASE CNT8 IS --CNT8是一个3位计数器，作扫描计数信号,位选择 WHEN "000" => BT <= "00000001" ; A <= d0 ; WHEN "001" => BT <= "00000010" ; A <= d1 ; WHEN "010" => BT <= "00000100" ; A <= d2; WHEN "011" => BT <= "00001000" ; A <= d3 ; WHEN "100" => BT <= "00010000" ; A <= d4; WHEN "101" => BT <= "00100000" ; A <= d5; WHEN "110" => BT <= "01000000" ; A <= d6; WHEN "111" => BT <= "10000000" ; A <= d7 ; WHEN OTHERS => NULL ; END CASE ; END PROCESS P1; P2:PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1; END IF; END PROCESS P2 ; P3:PROCESS( A ) BEGIN CASE A IS WHEN "0000"=> SG <= "0111111"; WHEN "0001" => SG <= "0000110"; WHEN "0010" => SG <= "1011011"; WHEN "0011" => SG <= "1001111"; WHEN "0100" => SG <= "1101101"; WHEN "0101" => SG <= "1111000"; WHEN "0110" => SG <= "1111101"; WHEN "0111" => SG <= "1110110"; WHEN "1000"=> SG <= "0111000"; WHEN "1001"=> SG <= "1010100"; WHEN "1010"=> SG <= "1110111"; WHEN "1011"=> SG <= "1111100"; WHEN "1100"=> SG <= "0111001"; WHEN "1101"=> SG <= "1011110"; WHEN "1110"=> SG <= "1111001"; WHEN "1111" => SG <= "1110001"; WHEN OTHERS => NULL ; END CASE ; END PROCESS P3; END; --状态机 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY color8 IS PORT(cLK,rst:IN std_LOGIC; sel:in std_LOGIC_VECTOR(1 DOWNTO 0); ABC:OUT std_LOGIC_VECTOR(3 DOWNTO 0) ); END color8; ARCHITECTURE color OF color8 IS TYPE state_1 IS (s0,s1,s2,s3,s4,s5); SIGNAL state_2:state_1; BEGIN pr_1:PROCESS (cLK,rst) BEGIN IF rst='1' THEN state_2<=s0; ELSIF cLK'event AND cLK='1' THEN CASE state_2 IS WHEN s0=> state_2<=s1; WHEN s1=> state_2<=s2; WHEN s2=> state_2<=s3; WHEN s3=> state_2<=s4; WHEN s4=> state_2<=s5; WHEN s5=> state_2<=s0; END CASE; END IF; END PROCESS pr_1; pr_2:PROCESS(sel,state_2) BEGIN if sel="00" then CASE state_2 IS WHEN s0=>ABC<="0000"; WHEN s1=> ABC<="0001"; WHEN s2=>ABC<="0010"; WHEN s3=> ABC<="0011"; WHEN s4=> ABC<="0100"; WHEN s5=> ABC<="0101"; END CASE; END IF; END PROCESS; END color; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ss IS PORT(cLK,rst:IN std_LOGIC; ABC:in std_LOGIC_VECTOR(3 DOWNTO 0); d0,d1,d2:out std_LOGIC_VECTOR(3 DOWNTO 0)); END ss; ARCHITECTURE color OF ss IS BEGIN PROCESS(ABC,cLK) BEGIN IF rst='1' THEN ELSIF clk'EVENT AND clk='1' THEN IF(ABC=0) THEN d1<="0000"; d2<="0000"; d0<="0000";END IF; IF(ABC=1) THEN d0<="0100"; d1<="0101"; d2<="1010";END IF; IF(ABC=2) THEN d0<="0001"; d1<="1011"; d2<="1100";END IF; IF(ABC=3) THEN d0<="0010"; d1<="1111"; d2<="0110";END IF; IF(ABC=4) THEN d0<="0011"; d1<="0111"; d2<="1000";END IF; IF(ABC=5) THEN d0<="1110"; d1<="1001"; d2<="1101";END IF; END IF; end PROCESS; END color; 0
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