[求助]Quartusii编译报错奇怪

0

发现一个很大的错误，就是case语句中，变量格式应为二进制，故应将‘d’改为‘b’；；；不过编译后仍然报相同的错误
即：
   case(shi)
    4'b0000:outshi<=7'b0111111;
    4'b0001:outshi<=7'b0000110;
    4'b0010:outshi<=7'b1011011;
    4'b0011:outshi<=7'b1001111;
    4'b0100:outshi<=7'b1100110;
    4'b0101:outshi<=7'b1101101;
    4'b0110:outshi<=7'b1111101;
    4'b0111:outshi<=7'b0000111;
    4'b1000:outshi<=7'b1111111;
    4'b1001:outshi<=7'b1101111;
    default:outshi<=7'b0;
   endcase
////////////////////////////////

  case(ge)
   4'b0000:outge<=7'b0111111;
   4'b0001:outge<=7'b0000110;
   4'b0010:outge<=7'b1011011;
   4'b0011:outge<=7'b1001111;
   4'b0100:outge<=7'b1100110;
   4'b0101:outge<=7'b1101101;
   4'b0110:outge<=7'b1111101;
   4'b0111:outge<=7'b0000111;
   4'b1000:outge<=7'b1111111;
   4'b1001:outge<=7'b1101111;
     default:outge<=7'b0;
  endcase 


/*****************完整代码，不知哪里有错？着急呀~*************************/
module time_down(outshi,outge,clkin);
 parameter set_time=99;
 output[6:0] outshi,outge;
 input clkin;
 reg[6:0] outshi,outge;
 reg[25:0] counter;
 reg[3:0] shi,ge;
 reg sec;
 integer num;
 initial
  begin
  num=set_time;
  counter=0;
  end
/***************************************************************************/
 always@(posedge clkin)
  begin
   counter=counter+1;
   if(counter==10000000)
   begin
    counter=0;
    sec=~sec;
    if(num==0)
     num<=set_time;
    else  num<=num-1;
   end
  end
/********************************************************************/
 always@(negedge sec)
  begin
   shi<=num/10;
   case(shi)
    4'b0000:outshi<=7'b0111111;
    4'b0001:outshi<=7'b0000110;
    4'b0010:outshi<=7'b1011011;
    4'b0011:outshi<=7'b1001111;
    4'b0100:outshi<=7'b1100110;
    4'b0101:outshi<=7'b1101101;
    4'b0110:outshi<=7'b1111101;
    4'b0111:outshi<=7'b0000111;
    4'b1000:outshi<=7'b1111111;
    4'b1001:outshi<=7'b1101111;
    default:outshi<=7'b0;
   endcase
 
  end
/****************************************************************/
 always@(negedge sec)
  begin
  ge<=num%10;
  case(ge)
   4'b0000:outge<=7'b0111111;
   4'b0001:outge<=7'b0000110;
   4'b0010:outge<=7'b1011011;
   4'b0011:outge<=7'b1001111;
   4'b0100:outge<=7'b1100110;
   4'b0101:outge<=7'b1101101;
   4'b0110:outge<=7'b1111101;
   4'b0111:outge<=7'b0000111;
   4'b1000:outge<=7'b1111111;
   4'b1001:outge<=7'b1101111;
     default:outge<=7'b0;
  endcase 
  end
endmodule