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*two stage op design .lib "f:hspicewendangjiafaqilogs353v.l" tt *xor 2 .subckt xor2 a b c d f mxorpa 1 a vdd vdd pch l=0.35u w=4u mxorpb f d 1 vdd pch l=0.35u w=4u mxorpc 2 b vdd vdd pch l=0.35u w=4u mxorpd f c 2 vdd pch l=0.35u w=4u mxorna f a 3 gnd nch l=0.35u w=2u mxornb 3 b gnd gnd nch l=0.35u w=2u mxornc f c 4 gnd nch l=0.35u w=2u mxornd 4 d gnd gnd nch l=0.35u w=2u .ends xor2 *and2 .subckt and2 a b f mandpa f a vdd vdd pch l=0.35u w=2u mandpb f b vdd vdd pch l=0.35u w=2u mandna f a 1 gnd nch l=0.35u w=2u mandnb 1 b gnd gnd nch l=0.35u w=2u .ends and2 *and3 .subckt and3 a b c f mandpa f a vdd vdd pch l=0.35u w=2u mandpb f b vdd vdd pch l=0.35u w=2u mandpc f c vdd vdd pch l=0.35u w=2u mandna f a 1 gnd nch l=0.35u w=3u mandnb 1 b 2 gnd nch l=0.35u w=3u mandnc 2 c gnd gnd nch l=0.35u w=3u .ends and3 *and4 .subckt and4 a b c d f mandpa f a vdd vdd pch l=0.35u w=2u mandpb f b vdd vdd pch l=0.35u w=2u mandpc f c vdd vdd pch l=0.35u w=2u mandpd f d vdd vdd pch l=0.35u w=2u mandna f a 1 gnd nch l=0.35u w=4u mandnb 1 b 2 gnd nch l=0.35u w=4u mandnc 2 c 3 gnd nch l=0.35u w=4u mandnd 3 d gnd gnd nch l=0.35u w=4u .ends and4 *or2 .subckt or2 a b f morpa 1 a vdd vdd pch l=0.35u w=4u morpb f b 1 vdd pch l=0.35u w=4u mna f a gnd gnd nch l=0.35u w=2u mnb f b gnd gnd nch l=0.35u w=2u .ends or2 *or3 .subckt or3 a b c f morpa 1 a vdd vdd pch l=0.35u w=6u morpb 2 b 1 vdd pch l=0.35u w=6u morpc f c 2 vdd pch l=0.35u w=6u mna f a gnd gnd nch l=0.35u w=2u mnb f b gnd gnd nch l=0.35u w=2u mnc f c gnd gnd nch l=0.35u w=2u .ends or3 *or4 .subckt or4 a b c d f morpa 1 a vdd vdd pch l=0.35u w=8u morpb 2 b 1 vdd pch l=0.35u w=8u morpc 3 c 2 vdd pch l=0.35u w=8u morpd f d 3 vdd pch l=0.35u w=8u mna f a gnd gnd nch l=0.35u w=2u mnb f b gnd gnd nch l=0.35u w=2u mnc f c gnd gnd nch l=0.35u w=2u mnd f d 0 0 nch l=0.35u w=2u .ends or4 *not .subckt not a f mnotpa f a vdd vdd pch l=0.35u w=2u mnotna f a gnd gnd nch l=0.35u w=1u .ends not *反相器 *or21 .subckt or21 a b f xor2 a b 1 or2 xnot 1 f not .ends or21 *2输入或门 *or31 .subckt or31 a b c f xor3 a b c 1 or3 xnot 1 f not .ends or31 *3输入或门 *or41 .subckt or41 a b c d f xor4 a b c d 1 or4 xnot 1 f not .ends or41 *4输入或门 *xor21 .subckt xor21 a b f xm a A5 not xn b B5 not xxor a b A5 B5 f xor2 .ends xor21 * 2输入异或门 *and21 .subckt and21 a b f xand2 a b 1 and2 xnot 1 f not .ends and21 *2输入与门 *and31 .subckt and31 a b c f xand3 a b c 1 and3 xnot 1 f not .ends and31 *3输入与门 *and41 .subckt and41 a b c d f xand4 a b c d 1 and4 xnot 1 f not .ends and41 *4输入与门 xxor211 a1 b1 p1 xor21 xxor212 a2 b2 p2 xor21 xxor213 a3 b3 p3 xor21 xxor214 a4 b4 p4 xor21 xand211 a1 b1 g1 and21 xand212 a2 b2 g2 and21 xand213 a3 b3 g3 and21 xand214 p1 c0 m0 and21 xor211 m0 g1 c1 or21 *进位C1 xand311 p2 p1 c0 m1 and31 xand215 p2 g1 m2 and21 xor312 g2 m1 m2 c2 or31 *进位C2 xand411 p3 p2 p1 c0 m3 and41 xand313 p3 p2 g1 m4 and31 xand216 p3 g2 m5 and21 xor412 m3 m4 m5 g3 c3 or41 *进位C3 xxor215 p1 c0 s1 xor21 *输出s1 xxor216 p2 c1 s2 xor21 *输出s2 xxor217 p3 c2 s3 xor21 *输出s3 xxor218 p4 c3 s4 xor21 *输出s4 .opt scale=0.05u .global vdd gnd vdd vdd 0 1.2 va1 a1 gnd pulse 1.2 1.2 20n 1f 1f 30n 100n va2 a2 gnd pulse 0 0 20n 1f 1f 30n 100n va3 a3 gnd pulse 0 0 20n 1f 1f 30n 100n va4 a4 gnd pulse 0 0 20n 1f 1f 30n 100n vb1 b1 gnd pulse 1.2 1.2 20n 1f 1f 30n 100n vb2 b2 gnd pulse 1.2 1.2 20 1f 1f 30n 100n vb3 b3 gnd pulse 0 0 20n 1f 1f 30n 100n vb4 b4 gnd pulse 1.2 1.2 20n 1f 1f 30n 100n vc0 c0 gnd pulse 0 0 4n 1f 1f 0n 100n .tran 1n 100n .plot tran v(s1) .plot tran v(s2) .plot tran v(s3) .plot tran v(s4) .end |
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