uart的顶层模块编译出现一个问题，求解答

module uart(clk,rst,data_tx,data_rx);
input data_rx,clk,rst;
output wire data_tx;
wire clk,rst,clk16,data_en,data_rx_over,
wire [7:0]data_rt;
uart_clk bps(.clk(clk),.rst(rst),.clk16(clk16));
uart_rx receiver(.clk16(clk16),.rst(rst),.data_rx(data_rx),
                 .data_en(data_en),.data_rx_over(data_rx_over),.data_t(data_rt));
uart_tx transeiver(.clk16(clk16),.rst(rst),.data_in(data_rt),
                  .data_tx_flag(data_tx_flag),.data_tx_over(data_tx_over),.data_tx(data_tx));
uart_clk controll(.clk16(clk16),.rst(rst),.data_rx_over(data_rx_over),
                  .data_tx_over(data_tx_over),.data_tx_flag(data_tx_flag),.data_en(data_en));
endmocule
这是自己写的uart顶层模块，编译有个问题请求大神解答：
Error (10170): Verilog HDL syntax error at uart.v(5) near text "wire";  expecting an identifier ("wire" is a reserved keyword )
这个是什么意思，怎么改？



补充内容 (2016-1-21 18:52):
这个语法错误不懂 求大神解答
Error (10170): Verilog HDL syntax error at uart.v(5) near text £
Error (10170): Verilog HDL syntax error at uart.v(5) near text "£";  expecting ";"
Error (10170): Verilog HDL syntax error at uart.v(5) near text »