【创龙TMS320C6748开发板试用】+两张图，看清时钟

2015-10-13 16:42:02 2728 TMS320C6748

0 一直在看例程，但现例程中没有时钟的配置程序，一开始也没有在意，现在把例程都试差不多了，反回来想想，有点费解。由于没有看视频，今天发现视频里有一节是讲时钟的，就下载下来看成了一下。还是挻详细的。原来时钟的配置在gel文件中。根据视频的讲解，做了下面两张图，算是把时钟部分的要点总结一下，再深入就是研究DSP的了，而我们这些只是会用就行了。以下是两个时钟PLL0与PLL1的产生。下面是两个时钟的一些参数。之于时钟的配置可以在gel文件中的device_PLL0与device_PLL1两个函数中。 device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) { unsigned int i=0; /* Clear PLL lock bit / CFGCHIP0 &= ~(0x00000010); / Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR / PLL0_PLLCTL &= ~(0x00000020); / PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon / PLL0_PLLCTL &= ~(0x00000200); / Set PLLEN=0 to put in bypass mode/ PLL0_PLLCTL &= ~(0x00000001); /wait for 4 cycles to allow PLLEN mux switches properly to bypass clock/ for(i=0; i / Select the Clock Mode bit 8 as External Clock or On Chip Oscilator/ PLL0_PLLCTL &= 0xFFFFFEFF; PLL0_PLLCTL \|= (CLKMODE << 8); /Clear PLLRST bit to reset the PLL / PLL0_PLLCTL &= ~(0x00000008); / Disable the PLL output/ PLL0_PLLCTL \|= (0x00000010); / PLL initialization sequence Power up the PLL by setting PWRDN bit set to 0 / PLL0_PLLCTL &= ~(0x00000002); / Enable the PLL output/ PLL0_PLLCTL &= ~(0x00000010); /PLL stabilisation time- take out this step , not required here when PLL in bypassmode/ for(i=0; i /Program the required multiplier value in PLLM/ PLL0_PLLM = PLLM; /If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio/ PLL0_POSTDIV = 0x8000 \| POSTDIV; /Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress/ while(PLL0_PLLSTAT & 0x1==1){} /Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default)./ PLL0_PLLDIV1 = 0x8000 \| PLLDIV1; // Fixed Ratio /1 PLL0_PLLDIV2 = 0x8000 \| PLLDIV2; // Fixed Ratio /2 PLL0_PLLDIV4 = 0x8000 \| (((PLLDIV1+1)4)-1); // Fixed Ratio /4 PLL0_PLLDIV6 = 0x8000 \| PLLDIV1; // Fixed Ratio /1 PLL0_PLLDIV3 = 0x8000 \| PLLDIV3; // Variable Ratio (EMIF) PLL0_PLLDIV7 = 0x8000 \| PLLDIV7; // Variable Ratio (RMII) /Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition./ PLL0_PLLCMD \|= 0x1; /Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment)./ while(PLL0_PLLSTAT & 0x1==1) { } /Wait for PLL to reset properly./ for(i=0; i /Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset/ PLL0_PLLCTL \|= 0x8; /Wait for PLL to lock./ for(i=0; i /Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode/ PLL0_PLLCTL \|= 0x1; } /******************************************************************************** DDR PLL1 init: ********************************************************************************/ device_PLL1(unsigned int PLLM,unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3 ) { unsigned int i=0; / Clear PLL lock bit / CFGCHIP3 &= ~(0x00000020); / Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR / PLL1_PLLCTL &= ~(0x00000020); / PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon / PLL1_PLLCTL &= ~(0x00000200); / Set PLLEN=0 to put in bypass mode/ PLL1_PLLCTL &= ~(0x00000001); /wait for 4 cycles to allow PLLEN mux switches properly to bypass clock/ for(i=0; i /Clear PLLRST bit to reset the PLL / PLL1_PLLCTL &= ~(0x00000008); / Disable the PLL output/ PLL1_PLLCTL \|= (0x00000010); / PLL initialization sequence Power up the PLL by setting PWRDN bit set to 0 / PLL1_PLLCTL &= ~(0x00000002); / Enable the PLL output/ PLL1_PLLCTL &= ~(0x00000010); /PLL stabilisation time- take out this step , not required here when PLL in bypassmode/ for(i=0; i /Program the required multiplier value in PLLM/ PLL1_PLLM = PLLM; /If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio/ PLL1_POSTDIV = 0x8000 \| POSTDIV; /Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress/ while(PLL1_PLLSTAT & 0x1==1){} /Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default)./ PLL1_PLLDIV1 = 0x8000 \| PLLDIV1; // DDR frequency (aka 2X_CLK) PLL1_PLLDIV2 = 0x8000 \| PLLDIV2; // Optional CFGCHIP3[ASYNC3_CLKSRC] clock source PLL1_PLLDIV3 = 0x8000 \| PLLDIV3; // Optional PLL0 clock source /Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition./ PLL1_PLLCMD \|= 0x1; /Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment)./ while(PLL1_PLLSTAT & 0x1==1) { } /Wait for PLL to reset properly / for(i=0; i /Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset/ PLL1_PLLCTL \|= 0x8; /Wait for PLL to lock. See PLL spec for PLL lock time/ for(i=0; i /Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode/ PLL1_PLLCTL \|= 0x1; } 复制代码* 其实gel文件中所做的工作还是很多的。之前用28335的时候没怎么在意gel文件，所有的配置都是在C程序中的，看来有必要学习一下gel文件了。 0
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