[问答]

求大师解答，想了一晚上了

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问答对人有帮助，内容完整，我也想知道答案 0 Library ieee; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned; entity water_lamp is generic(n:integer:=48000000); port( clk:in std_logic; swich:in std_logic_vector(2 downto 0); Led:out std_logic_vector(2 downto 0) ); end water_lamp; architecture liushuideng of water_lamp is signal cnt:integer range 0 to n; signal clk_new:std_logic; signal *:integer range 0 to 2; begin process(clk) IS begin IF clk'event and clk='1' then if cnt cnt<=cnt+1; else cnt<=0; clk_new<=not clk_new; end if; end if; end process; process(clk_new) IS begin IF clk'event and clk='1' then IF <5 then <=+1; else <=0; end if; end if; end process ; process() IS begin IF swich="000" then Led<="000"; elsif swich="111" then led<="111"; elsif swich="001" then case is when 0=>led<="001"; when 1=>led<="010"; when 2=>led<="100"; when 3=>led<="111"; when 4=>led<="111"; when others=>led<="111"; end case; else swich="010" then case * is when 0=>led<="100"; when 1=>led<="010"; when 2=>led<="001"; when 3=>led<="111"; when 4=>led<="111"; when others=>led<="111"; end case; end if; end process ; end architecture liushuideng; 编译时出现Error (10500): VHDL syntax error at water_lamp.vhd(50) near text "="; expecting "(", or "'", or "." Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 427 megabytes Error: Processing ended: Sun Apr 12 11:46:24 2015 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings 哪位大神能帮忙解答下感激不禁 0
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