【求助】关于Modesim的添加信号问题

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity divclk1 is
  port(
       clk:in std_logic;
       divclk:out std_logic
      );
end divclk1;

architecture arch of divclk1 is
signal counter:std_logic_vector(4 downto 0):="00000";
signal tempdivclk:std_logic:='0';
begin
process(clk)
begin
  if clk'event and clk='1' then
    if (counter>="11000") then
      counter<="00000";
      tempdivclk<=not tempdivclk;
    else
      counter<=counter+'1';
    end if;
  end if;
end process;
divclk<=tempdivclk;
end arch;
----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity divclk1_tb is
end divclk1_tb;

architecture behavior of divclk1_tb is
  component divclk1
  port(
       clk:in std_logic;
       divclk:out std_logic
      );
  end component;
  signal clk:std_logic:='0';
  signal divclk:std_logic;
  begin
    uut:divclk1 port map (
    clk=>clk,divclk=>divclk);

    clk<=not clk after 10 ns;
  end behavior;
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用Modelsim仿真一个分频器，按照教程一步一步来，仿真divclk1_tb时，object串口只有clk一个信号，没有divclk，所以我就没法把divclk添加到wave窗口，这是怎么回事？我用的是modelsim se 10.1a版本