本人正在FPGA入门道路上裸奔的小白一枚,写了一段流水灯代码,四种流动模式,其中一种是来回流动的那种,但是总是出现这两行警告,接上LED灯之后输出还不对
Warning (10240): Verilog HDL Always Construct warning at runhorse_led_4_2.v(95): inferring latch(es) for variable "loop_bit_A", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at runhorse_led_4_2.v(95): inferring latch(es) for variable "counter_A", which holds its previous value in one or more paths through the always construct
下面是出问题的那段代码,求大大们指教啊,我已经快要被逼疯了
always @ (posedge clk_led_in or negedge rst)
begin
case (SW_AB_led)
model0:
begin
decoder_2_4 (counter_A, led_data_r);
if (!rst)
begin
loop_bit_A = 1'b0;
counter_A = 2'b0;
end
else if (loop_bit_A)
begin
counter_A = counter_A + 1'b1;
if (counter_A==2'b11)
loop_bit_A = 1'b0;
end
else
begin
counter_A = counter_A - 1'b1;
if (counter_A==2'b0)
loop_bit_A = 1'b0;
end
end
我在外面定义了一个2-4译码器的任务,就是“decoder_2_4 (counter_A, led_data_r);”那行,我的想法是只要counter_A在2’b0到2‘b11之间来回跑就行了,但是~~~~~~~
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
begin
current_state <= 0;
delay <= 0;
// data_reg <= 0;
end
else begin
case(current_state)
idle: begin
if(delay<10)
begin delay <= delay+16'd1; end
else begin
current_state <= next_state;
delay <= 0; end
end
start: begin
current_state <= next_state;
end
start_wait: begin
current_state <= next_state;
end
convert: begin
if(delay<2) begin
delay <= delay+16'd1; end
else begin
// data_reg <= data;
current_state <= next_state;
delay <= 0; end
end
default: ;
endcase
end
end
// always @ (current_state or intr_n or rst_n) begin
always @ (current_state or rst_n) begin
if(!rst_n) begin
idle <= 0;
start <= 1;
start_wait <= 2;
convert <= 3;
// read_flag <= 0;
end
else begin
case (current_state)
idle: begin
cs_n <= 1;
wr_n <= 1;
rd_n <= 1;
// read_flag <= 0;
next_state <= start; end
start: begin
cs_n <= 0;
wr_n <= 0;
rd_n <= 1;
// read_flag <= 0;
next_state <= start_wait; end
start_wait: begin
wr_n <= 1;
cs_n <= 1;
rd_n <= 1;
// read_flag <= 0;
// if(!intr_n) next_state <= convert;
// else
next_state <= start_wait;
end
convert: begin
cs_n <= 0;
rd_n <= 0;
wr_n <= 1;
// read_flag <= 1;
next_state <= idle; end
default: next_state <= idle;
endcase
end
end
/************************************** */