lcd驱动程序，分频电路为何必须是分好多次才可以

FPGA

大家好，本人初学FPGA，最近在学习lcd驱动程序，里面的分频电路为何必须是分好多次才可以，直接产生一个周期为5ms的时钟不可以吗
原始分频：

reg [8:0] count;
reg clk_div1;    //500个clk的周期，20ns*500=10us
reg clk_div2;    //1000个，20us
reg [7:0] count1; //250个clk_div2的周期，20us*250=5000u=5ms
reg clk_buf;
//******************
//-----分频模块-----
//******************
always @(posedge clk or negedge rst)
begin
if(!rst) //rst=0
      count<=0;
else
      begin
         if(count<250)       //2500
            begin
                  clk_div1<=0;
                  count<=count+1'b1;
            end
         else if(count>=500-1)       //5000
            count<=0;
         else
            begin
                  clk_div1<=1;
                  count<=count+1'b1;
            end
      end
end
always @(posedge clk_div1 or negedge rst)
begin
if(!rst)
      clk_div2<=0;
else
      clk_div2<=~clk_div2;
end
always @(posedge clk_div2 or negedge rst)
begin
if(!rst) //rst=0
      begin
         count1<=0;
         clk_buf<=0;    //
      end
else
      begin
         if(count1<125)    //2500
            begin
                  clk_buf<=0;
                  count1<=count1+1'b1;
            end
         else if(count1>=250-1)    //5000
            count1<=0;
         else
            begin
                  clk_buf<=1;
                  count1<=count1+1'b1;
            end
      end
end

这样为何不行？

reg clk_div;
reg[17:0] count;
always@(posedge clk or negedge rst)
      if(rst==0)
         clk_div<=0;
      else if(count<=125000)
               begin
               clk_div<=0;
                              count<=count+1;
                              end
                     else if(count>250000-1)
                              begin
                              clk_div<=0;
                              count<=0;
                                       end
                                       else
                                       clk_div<=1;