[求助]

1010时序检测器，用verilog做，在线等大牛帮助，谢谢

2014-3-26 14:52:27 4155

0 要求：在ICEcube2 中任选一款芯片，在选择的芯片上设计一个二进制序列检测器，当检测到1010序列时，计数器加1，规定检测到一次之后，检测器不必回到最初状态，比如序列0110101011，检测器应该检测到2个1010序列而不是1个。输入信号：clk，reset，serial_data(数据宽度1bit，即串行输入)；输出信号：count(数据宽度3bit) 激励（serial_data的数据, 仿真时须要用这段输入数据）：0110101011011001010111101010101101；下面是我的source code, 用状态机做的（重点帮我看一下“go to next state”是否正确） `timescale 1ns / 1ps module serDetect1010(serial_data, clk, reset, counter); input serial_data; input clk; input reset; output [2:0] counter; reg [2:0] counter; reg [3:0] state, nstate; //state parameter parameter IDLE = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0101, S4 = 4'b1010; //go to next state always@(state or serial_data) begin case(state) IDLE: if(serial_data==1) nstate <= S1; else nstate <= IDLE; S1: if(serial_data==0) nstate <= S2; else nstate <= S1; S2: if(serial_data==1) nstate <= S3; else nstate <= IDLE; S3: if(serial_data==0) nstate <= S4; else nstate <= S1; S4: if(serial_data==1) nstate <= S3; else nstate <= IDLE; endcase end //update state always@(posedge clk or negedge reset) begin if(!reset) state <= IDLE; else state <= nstate; end //counter always@(state or reset or serial_data) begin if(!reset) counter = 0; else if(state===S4) counter = counter+1; //else // counter = counter+0; end endmodule 0 问题时序图.png (151.64 KB, 下载次数: ) 问题时序图.png (151.64 KB, 下载次数: )
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0 这个是我的test bench: `timescale 1ns / 1ps module TsTserDetect1010_v; // Inputs reg serial_data; reg clk; reg reset; // Outputs wire [2:0] counter; // Instantiate the Unit Under Test (UUT) serDetect1010 uut ( .serial_data(serial_data), .clk(clk), .reset(reset), .counter(counter) ); initial begin // Initialize Inputs serial_data = 0; clk = 0; reset = 1; // Wait 100 ns for global reset to finish #22 reset = 0; #133 reset = 1; // Add stimulus here //serial_data = 64'b0110 1010 1101 1001 0101 1110 1010 1011 01; #80 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #100 serial_data = 1'b1; #100 serial_data = 1'b0; #100 serial_data = 1'b1; #4000 $stop; end always #50 clk = ~clk; //simulation clk always@(posedge clk or negedge reset) begin end endmodule

2014-3-26 14:53:55 评论举报 1^# Seapol