[经验]

verilog编写AD7606串行接受数据，但是还没有接通，求高手指教

2014-3-18 19:29:15

4437

verilog程序：

module ad1(clk,busy,sclk,convst,db,cs,in);
output reg convst;
output reg cs;
input busy,in;
output reg sclk;
input clk;
output reg [15:0] db;
reg [4:0] state;
reg flag;
reg [15:0] data,ad_out;

always @(negedge clk)
begin
case (state)
5'b00000 :
  begin
convst<=0;
state<=5'b00001;
cs<=1;
sclk<=1;
data<=0;
ad_out<=0;
  end
5'b00001 :
  begin
convst<=1;
state<=5'b00010;
cs<=1;
sclk<=1;
  end
5'b00010 :
  begin
if (busy)
state<=5'b00010;
else
begin
   state<=5'b00011;
   convst<=1;
   cs<=1;
   sclk<=1;
end
  end
5'b00011 :
  begin
sclk<=0;
convst<=1;
cs<=0;
state<=5'b00100;
sclk<=1;
flag<=0;
  end
5'b00100 :
  begin
if (flag==0)
begin
   state<=5'b00100;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<15);
   sclk<=1;
end
else
begin
   state<=5'b00101;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
end
5'b00101 :
  begin
if (flag==0)
begin
   state<=5'b00101;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<14);
   sclk<=1;
end
else
begin
   state<=5'b00110;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b00110 :
  begin
if (flag==0)
begin
   state<=5'b00110;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<13);
   sclk<=1;
end
else
begin
   state<=5'b00111;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b00111 :
  begin
if (flag==0)
begin
   state<=5'b00111;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<12);
   sclk<=1;
end
else
begin
   state<=5'b01000;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01000 :
  begin
if (flag==0)
begin
   state<=5'b01000;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<11);
   sclk<=1;
end
else
begin
   state<=5'b01001;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01001 :
  begin
if (flag==0)
begin
   state<=5'b01001;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<10);
   sclk<=1;
end
else
begin
   state<=5'b01010;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01010 :
  begin
if (flag==0)
begin
   state<=5'b01010;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<9);
   sclk<=1;
end
else
begin
   state<=5'b01011;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01011 :
  begin
if (flag==0)
begin
   state<=5'b01011;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<8);
   sclk<=1;
end
else
begin
   state<=5'b01100;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01100 :
  begin
if (flag==0)
begin
   state<=5'b01100;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<7);
   sclk<=1;
end
else
begin
   state<=5'b01101;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01101 :
  begin
if (flag==0)
begin
   state<=5'b01101;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<6);
   sclk<=1;
end
else
begin
   state<=5'b01110;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01110 :
  begin
if (flag==0)
begin
   state<=5'b01110;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<5);
   sclk<=1;
end
else
begin
   state<=5'b01111;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b01111 :
  begin
if (flag==0)
begin
   state<=5'b01111;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<4);
   sclk<=1;
end
else
begin
   state<=5'b10000;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b10000 :
  begin
if (flag==0)
begin
   state<=5'b10000;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<3);
   sclk<=1;
end
else
begin
   state<=5'b10001;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b10001 :
  begin
if (flag==0)
begin
   state<=5'b10001;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<2);
   sclk<=1;
end
else
begin
   state<=5'b10010;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b10010 :
  begin
if (flag==0)
begin
   state<=5'b10010;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=(in<<1);
   sclk<=1;
end
else
begin
   state<=5'b10011;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   sclk<=0;
end
  end
5'b10011 :
  begin
if (flag==0)
begin
   state<=5'b10011;
   convst<=1;
   cs<=0;
   flag<=1;
   data<=in;
   sclk<=1;
end
else
begin
   state<=5'b00000;
   convst<=1;
   cs<=0;
   flag<=0;
   ad_out<=ad_out+data;
   db<=ad_out;
   sclk<=0;
end
  end
endcase
end
endmodule