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请教大家一个问题, 我写了一个状态机,代码如下: always @(posedge p0rxc or negedge rst_n) begin if(!rst_n) current_state <= idle; else current_state <= next_state; end always @(current_state) begin case(current_state) idle : if(read_fifo_empty) next_state <= idle; else if(start_read_fifo) next_state <= first_read; else next_state <= idle; first_read : if(read_fifo_cnt == 16'd7) next_state <= judge_data_type; else next_state <= first_read; judge_data_type : if(video_data_type) next_state <= judge_video_range; else next_state <= judge_cardNo; judge_video_range : next_state <= local_forward; judge_cardNo : next_state <= local_forward; local_forward : if(forward_video||forward_notvideo||forward_frame) next_state <= forward; else next_state <= local; local : if(read_fifo_empty) next_state <= idle; else next_state <= local; forward : if(read_fifo_empty) next_state <= idle; else next_state <= forward; default : next_state <= idle; endcase end 这个状态机下载到FPGA是能正常工作的。 问题是在Isim仿真中,当read_fifo_empty=0而start_read_fifo=1时,curent_state为什么不跳转到first_read。如图1.
图1 状态不转变 然后我将状态机修改如下,再仿真可以看到状态机跳转了。如图2. always @(posedge p0rxc or negedge rst_n) begin case(current_state) idle : if(read_fifo_empty) current_state <= idle; else if(start_read_fifo) current_state <= first_read; else current_state <= idle; first_read : if(read_fifo_cnt == 16'd7) current_state <= judge_data_type; else current_state <= first_read; judge_data_type : if(video_data_type) current_state <= judge_video_range; else current_state <= judge_cardNo; judge_video_range : current_state <= local_forward; judge_cardNo : current_state <= local_forward; local_forward : if(forward_video||forward_notvideo||forward_frame) current_state <= forward; else current_state <= local; local : if(read_fifo_empty) current_state <= idle; else current_state <= local; forward : if(read_fifo_empty) current_state <= idle; else current_state <= forward; default : current_state <= idle; endcase end
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