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想做一个256*1的异步FIFO,这里只写了写的程序,
module myfifo(clk_1,indata,clk_2,outdata); input clk_1; //write clock// input indata; //input data// output clk_2; //read clock// output outdata; // output data// parameter DEPTH=256,MAX_COUNT=8'b11111111; //256*1// reg emptyp=1'b1; //empty flag// reg fullp=1'b0; //full flag// reg outdata; reg[DEPTH-1:0] tail=8'b00000000; //tail pointer// reg[DEPTH-1:0] head=8'b00000000; //head pointer// reg fifomem[0:MAX_COUNT]; //define the memory// //write// always @(posedge clk_1) begin if(emptyp==1'b1) if(head==DEPTH-1) fifomem[head]<=indata; emptyp<=1'b0; fullp<=1'b1; else fifomem[head]<=indata; head<=head+1; end endmodule 编译出来有这样的错误Error (10170): Verilog HDL syntax error at myfifo.v(24) near text "else"; expecting "@", or "end", or an identifier ("else" is a reserved keyword ), or a system task, or "{", or a sequential statement 改了很久,也不知道是什么问题 |
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