摘要:针对FPGA/CPLD同步设计过程中一些容易被忽视的问题进行了研究,分析了问题产 生的原因、对可靠性的影响,并给出了解决方案。 关键词:FPGA/CPLD;同步设计;时钟;亚稳态 Abstract:This paper is focused on some easy neglected problems in synchronous design for FP— GA/CPLD,analyzing the reasons and it’S influences on reliability,and giving the solutions. Key words:FPGA/CPLD;Synchronous design;Clock;Metastable state