ise 错误，求解决办法

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    15:42:41 09/03/2013
// Design Name:
// Module Name:    mycoeff
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mycoeff(
    input clk,
    input reset,
    input [15:0] x_in,
    input [15:0] e_in,
    output [127:0] w_out
    );
  
   reg [127:0] deltaw;
reg [127:0] x_in_temp;
reg [127:0] e_in_temp;
wire [127:0] w;
//
wire [47:0] m0_out,m1_out,m2_out,m3_out;
wire [47:0] m4_out,m5_out,m6_out,m7_out;
//
always @(posedge clk) begin
  if(reset) begin
   x_in_temp<=0;
   e_in_temp<=0;
  end
    else begin
     x_in_temp[127:0]<={x_in,x_in_temp[127:16]};
   e_in_temp[127:0]<={e_in,e_in_temp[127:16]};
  end
assign w_out=w;
assign w[15:0]=reset?16'h0000:m0_out[15:0];
assign w[31:16]=reset?16'h0000:m1_out[15:0];
assign w[47:32]=reset?16'h0000:m2_out[15:0];
assign w[63:48]=reset?16'h0000:m3_out[15:0];
assign w[79:64]=reset?16'h0000:m4_out[15:0];
assign w[95:80]=reset?16'h0000:m5_out[15:0];
assign w[111:96]=reset?16'h0000:m6_out[15:0];
assign w[127:112]=reset?16'h0000:m7_out[15:0];
mult1 mult1_0(
.A_IN(x_in_temp[31:16]),
.B_IN(e_in_temp[31:16]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[15]}},w[15:0]}),
.RST_IN(reset),
.P_OUT(m0_out)
);
mult1 mult1_1(
.A_IN(x_in_temp[31:16]),
.B_IN(e_in_temp[31:16]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[131]}},w[31:16]}),
.RST_IN(reset),
.P_OUT(m1_out));
mult1 mult1_2(
.A_IN(x_in_temp[47:32]),
.B_IN(e_in_temp[47:32]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[47]}},w[47:32]}),
.RST_IN(reset),
.P_OUT(m2_out));
mult1 mult1_3(
.A_IN(x_in_temp[63:48]),
.B_IN(e_in_temp[63:48]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[63]}},w[63:48]}),
.RST_IN(reset),
.P_OUT(m3_out));
mult1 mult1_4(
.A_IN(x_in_temp[79:64]),
.B_IN(e_in_temp[79:64]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[79]}},w[79:64]}),
.RST_IN(reset),
.P_OUT(m4_out));
mult1 mult1_5(
.A_IN(x_in_temp[95:80]),
.B_IN(e_in_temp[95:80]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[95]}},w[95:80]}),
.RST_IN(reset),
.P_OUT(m5_out));
mult1 mult1_6(
.A_IN(x_in_temp[111:96]),
.B_IN(e_in_temp[111:96]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[111]}},w[111:96]}),
.RST_IN(reset),
.P_OUT(m6_out));
mult1 mult1_7(
.A_IN(x_in_temp[127:112]),
.B_IN(e_in_temp[127:112]),
.CE_IN(!reset),
.CLK_IN(clk),
.C_IN({{32{w[127]}},w[127:112]}),
.RST_IN(reset),
.P_OUT(m7_out)
);
endmodule

提示错误：
ERROR:HDLCompiler:806 - "C:/Documents and Settings/proj1/mycoeff.v" Line 130: Syntax error near "endmodule".
ERROR:ProjectMgmt:497 - 1 error(s) found while parsing design hierarchy.

该怎么解决?实在找不出问题原因