CPLD程序代码仿真出现问题，请各位大侠帮帮忙，谢谢

Library IEEE;
USE IEEE.STD_logic_1164.all;
USE IEEE.STD_logic_unsigned.all;
ENtiTY code IS
PORT(en:in std_logic;
data  :in std_logic;
clk:in std_logic;
clr:in std_logic;
code_out  :out std_logic;
clk2x : out std_logic
);
END code;
ARCHITECTURE code OF code IS
SIGNAL clk1,clk2,mo:std_logic;
SIGNAL count_m100   :std_logic_vector(6 downto 0);
SIGNAL cnt   :std_logic_vector(2 downto 0);
SIGNAL shift_r     :std_logic_vector(2 downto 0);
begin
----------------分频器--------------------------
process(clk)
begin
       if(clk'event and clk='1')then
         cnt<=cnt+1;
       end if;
  --if(clr='1') then
   --clk2<='0';
  --elsif(en ='1')then
   --clk2<=not(clk2);
  --end if;
--end if;
end process;
clk2<=cnt(0);
clk2x<=clk2;
-------------------------------------
process(clk,en,clr)
begin
if(clr='1')then
  count_m100<="0000000";
elsif(clk'event and clk='1')then
  if(count_m100="1100011")then       --0-99 100次
   count_m100<="0000000";
  elsif(en='1')then
   count_m100<=count_m100+'1';
  end if;
end if;
end process;
---------------------------------
process(clk2,en,clr)
begin
if(clr='1')then
  shift_r<=(others=>'0');
elsif(clk2'event and clk2='1')then
  if(en='1')then
   shift_r<=shift_r(1 downto 0)&data;
  end if;
end if;
end process;

---------------------------------------------
process(clk,clk2,count_m100,en,clr,mo,shift_r)
begin
if(clr='1')then
  mo<='1';
elsif(count_m100>="0000001" and count_m100<="0000010")then  --1-2
     mo<='0';
     elsif(count_m100>="0000011" and count_m100<="1100010")then --3-98
        mo<=shift_r(2) XOR clk2;
        else
        mo<='0';
     end if;
end process;
END code;
      问题：仿真时data数据如果是0时异或不起作用，一直保持前一个状态，请各位大侠帮帮忙，再次感谢！！！！