在配置ADAR7251后，AD_fault=0，通过读取寄存器信息，总是提示Clock Loss Error的原因？

在配置ADAR7251后，AD_fault=0，通过读取寄存器信息，总是提示Clock Loss Error，请问这是什么原因造成的。
配置方式如下：时钟选取30MHz，采用master 串行工作模式
4'd0://CLOCK CONTROL REGISTER
   begin
   spi_addr<=16'h0000;//Uses the PLL output for the internal master clock, or bypasses the PLL
   spi_in<=16'h0001;//CLK_CTRL=1
   end
   4'd1://PLL DENOMINATOR REGISTER
   begin
   spi_addr<=16'h0001;//Sets the 16-bit denominator of the fractional part (M)
   spi_in<=16'h0064;////PLL_DEN=100
   end
   4'd2://PLL NUMERATOR REGISTER
   begin
   spi_addr<=16'h0002;//Sets the 16-bit numerator of the fractional part (N)
   spi_in<=16'h0054;//PLL_NUM==84
   end
   4'd3://PLL CONTROL REGISTER
   begin
   spi_addr<=16'h0003;//Sets the PLL mode, PLL enable, 4-bit integer multiplier (R), and 4-bit integer divider (X)
   spi_in<=16'h3813;//PLL_CTRL=0x3813
   end
   4'd4://POWER ENABLE REGISTER
   begin
   spi_addr<=16'h0042;//POWER_ENABLE
   spi_in<=16'h03FF;//
   end
   4'd5://MASTER ENABLE SWITCH REGISTER
   begin
   spi_addr<=16'h0040;//Master Enable Switch.
   spi_in<=16'h0001;//MASTER_ENABLE=1
   end
   4'd6://SIGNAL PATH FOR ADC 1 THROUGH ADC 4 REGISTER
   begin
   spi_addr<=16'h0102;//LNA PGA EQ Path.
   spi_in<=16'h2222;//LNA PGA Path (Bypass EQ).
   end
   4'd7://DECIMATOR RATE CONTROL REGISTER
   begin
   spi_addr<=16'h0140;//DECIM_RATE
   spi_in<=16'h0003;//0,1==not use;2=1.8MSPS;3=1.2MSPS;4=900KSPS;5=600KSPS;6=450KSPS;7=300KSPS;
   end
   4'd8://HIGH PASS FILTER CONTROL REGISTER
   begin
   spi_addr<=16'h0141;//HIGH_PASS
   spi_in<=16'h0018;
   end
   4'd9://SERIAL OUTPUT PORT CONTROL REGISTER
   begin
   spi_addr<=16'h01c0;//SERIAL_MODE
   spi_in<=16'h0040;//master
   end
   4'd10://ADC DIGITAL OUTPUT MODE REGISTER
   begin
   spi_addr<=16'h01c2;//OUTPUT_MODE
   spi_in<=16'h0002;//CONV_START Function is Disabled
   end
   4'd11://ADC TEST REGISTER
   begin
   spi_addr<=16'h0301;//ADC_SETTING1
   spi_in<=16'h0304;
   end
   4'd12://ADC TEST REGISTER
   begin
   spi_addr<=16'h0308;//ADC_SETTING2
   spi_in<=16'h0000;
   end
   4'd13://DIGITAL FILTER SYNC ENABLE REGISTER
   begin
   spi_addr<=16'h030e;//DEJITTER_WINDOW
   spi_in<=16'h0000;//Digital Filter Sync Disable
   end
   4'd14:///CLOCK CONTROL REGISTER
   begin
   spi_addr<=16'h0000;//Uses the PLL output for the internal master clock, or bypasses the PLL
   spi_in<=16'h0000;//CLK_CTRL=0
   end