【设计进展】基于FPGA的温控风扇（补充）

元件

具体更新贴，我再上传了一次因为刚刚传了不图！！sorry！

这个学期的期末考试快到了，忙于复习，所以更新慢了，希望大家见谅。现在上传有关温度传感器的设计进程吧。
我们决定采用数字式的集成温度传感器DS18B20作为温度检测的核心元件，由其检测并直接输出数字温度信号给FPGA进行处理。原因是数字式集成温度传感器DS18B20的高度集成化，大大降低了外接放大转化等电路的误差因数，温度误差变得很小，并且由于其检测温度的原理与热敏电阻检测的原理有着本质的不同，使得其温度分辨力极高。温度值在器件内部转化成数字量直接输出，简化了系统程序设计，又由于该温度传感器采用先进的单总线技术，与FPGA的接口变得非常简洁，抗干扰能力强，因此该方案适用于本系统。（关于DS18B20的资料我这里就不发上来了，网上很好找）

硬件方面
我们预想是多点采集温度信号，再把信号送到FPGA进行处理，这样做令测量到的温度更加精确。DS18B20采用的是外部供电方式。原理图如下：

软件方面
现在仿真通过的只有3个小模块，其他在调试中，分别是重启DS18B20、写与读单字节

重启模块
reg Flag_Rst;       //复位完成标志
reg [4:0] Rststate;       //复位状态(待修改)
reg [10:1] CountRstStep;    //复位计数器 1024
task Rst_DS18B20; begin
case(Rststate)
state_0 :       //out 1 ,keep 1us
begin
  Flag_Rst <= 0;    //复位进行中
  icdata <= 16'b1111_1111_1111_1111;  //总线拉高16'b1111_1111_1111_1111
  Rststate <= state_1;
  CountRstStep <= 0;
end
state_1 :
begin
  icdata <= 0;    //总线拉低
  if(CountRstStep > 600)    //拉低时间600us
  begin
CountRstStep <= 0;    //计数器清0
Rststate <= state_2;
  end
  else
  begin
CountRstStep <= CountRstStep + 1;
Rststate <= state_1; //计时未到
  end
end
state_2 : //此阶段为等待阶段
begin
  icdata <= 16'b1111_1111_1111_1111;    //FPGA将总线拉高，为下一阶段DS18B20响应做准备
  if(CountRstStep > 50)    //拉高时间50us
  begin
CountRstStep <= 0;    //计数器清0
Rststate <= state_3;
  end
  else
  begin
CountRstStep <= CountRstStep + 1;
Rststate <= state_2; //计时未到
  end
end
state_3 :
begin
  icdata <= 16'bzzzz_zzzz_zzzz_zzzz;    //释放总线，等待DS18B20响应
  Rststate <= state_4;
end
state_4 :
begin
  if(icdata == 16'b0000_0000_0000_0000)    //初始化完成
  begin
   if(CountRstStep > 100)
   begin
CountRstStep <= 0;
Rststate <= state_5; //结束
end
else
begin
CountRstStep <= CountRstStep + 1;
Rststate <= state_4;
end
  end
  else    //等不到DS18B20响应，50us返回状态0
  begin
if(CountRstStep > 50)
begin
CountRstStep <= 0;
Rststate <= state_0; //state_0
end
else
begin
CountRstStep <= CountRstStep + 1;
Rststate <= state_4;
end
  end
end
state_5 :
  icdata <= 16'b1111_1111_1111_1111; //FPGA拉高总线

state_6 :
begin
  if(CountRstStep == 200)//总线电平拉高后，还需要保持高电平200us
  begin
CountRstStep <= 0;
Rststate <= state_7;
  end
  else
  begin
CountRstStep <= CountRstStep + 1;
Rststate <= state_6;
  end
end
state_7 :
begin
  Flag_Rst <= 1;    //初始化完成
  CountRstStep <= 0;
  Rststate <= state_0;    //回到原点
end
default :
begin
  Rststate <= state_0;
  CountRstStep <= 0;
end
endcase
end
endtask

写单字节模块
reg Flag_wBit;       //写位完成标志
reg[4:0] WriteBitstate;    //写位命令状态
reg[8:1] CountWbitStep;    //写位计数器
task wBit_DS18B20;
input wiBit;       //位信息
begin
case(WriteBitstate)
state_0 :
begin
  Flag_wBit <= 0;    //写位进行中
  icdata <= 16'b1111_1111_1111_1111;
  WriteBitstate <= state_1;
  CountWbitStep <= 0;
end
state_1 :
begin
  icdata <= 0;    //总线拉低
  if(wiBit) WriteBitstate <= state_2;  //写1的命令
  else WriteBitstate <= state_4; //写0的命令
end
state_2 :
begin
  if(CountWbitStep >= 3)    //维持高电平3us,为每次写位指令之间留出3us的间隔
  begin
CountWbitStep <= 0;
icdata <= 16'b1111_1111_1111_1111;
WriteBitstate <= state_3;
  end
  else
  begin
CountWbitStep <= CountWbitStep + 1;
WriteBitstate <= state_2;
  end
end
state_3 :
begin
  if(CountWbitStep >= 60)    //维持拉高电平60us
  begin
CountWbitStep <= 0;
WriteBitstate <= state_6;
  end
  else
  begin
CountWbitStep <= CountWbitStep + 1;
WriteBitstate <= state_3;
  end
end
state_4 :
begin
  if(CountWbitStep >= 60)    //维持低电平60us
  begin
CountWbitStep <= 0;
WriteBitstate <= state_5;
  end
  else
  begin
icdata <= 0;
CountWbitStep <= CountWbitStep + 1;
WriteBitstate <= state_4;
  end
end
state_5 :
begin
  if(CountWbitStep >= 3)    //拉高总线3us,为每次写位指令之间留出3us的间隔
  begin
CountWbitStep <= 0;
WriteBitstate <= state_6;
  end
  else
  begin
icdata <= 16'b1111_1111_1111_1111;
CountWbitStep <= CountWbitStep + 1;
WriteBitstate <= state_5;
  end
end
state_6 :
begin
  Flag_wBit <= 1;    //写位命令完毕
  CountWbitStep <= 0;
  WriteBitstate <= state_0;
end
default :
begin
  Flag_wBit <= 0;
  CountWbitStep <= 0;
  WriteBitstate <= state_0;
end
endcase
end
endtask

读单字节模块
reg Flag_rBit;       //读位命令标志
reg[4:0] ReadBitstate;    //读位命令状态
reg[6:1] CountRbitStep;    //读位命令计时器
task rBit_DS18B20;
begin
case(ReadBitstate)
state_0 :
begin
  Flag_rBit <= 0;    //读位命令进行中
  icdata <= 16'b1111_1111_1111_1111;
  CountRbitStep <= 0;
  ReadBitstate <= state_1;
end
state_1 :
begin
  if(CountRbitStep >= 3)    //保持低电平3us
  begin
icdata <= 16'b1111_1111_1111_1111;             //先将总线拉高，再释放总线
icdata <= 16'bzzzz_zzzz_zzzz_zzzz;    //改为输入
CountRbitStep <= 0;
ReadBitstate <= state_2;
  end
  else
  begin
icdata <= 0;    //总线拉低
CountRbitStep <= CountRbitStep + 1;
ReadBitstate <= state_1;
  end
end
state_2 :
begin
  if(CountRbitStep >= 10)    //维持输入状态10us，就读取总线上的信息
  begin
temp[j] <= icdata;                   //temp[]数组保存读取的数据
CountRbitStep <= 0;
ReadBitstate <= state_3;
  end
  else
  begin
CountRbitStep <= CountRbitStep + 1;
ReadBitstate <= state_2;
  end
end
state_3 :
begin
  if(CountRbitStep >= 60)    //维持60us输入
  begin
CountRbitStep <= 0;
ReadBitstate <= state_4;
  end
  else
  begin
CountRbitStep <= CountRbitStep + 1;
ReadBitstate <= state_3;
  end
end
state_4 :
begin
  Flag_rBit <= 1;    //读位命令完毕
  CountRbitStep <= 0;
  ReadBitstate <= state_0;
end
default :
begin
  Flag_rBit <= 0;
  CountRbitStep <= 0;
  ReadBitstate <= state_0;
end
endcase
end
endtask