理解不了这段汉明 解码器代码（in Verilog）？

问题在截图里，图片压缩的话可以去上传的文件看看。
非常需要帮助，谢谢。

module Vrhamcorr64(DU, DC, NOERROR, UCERR);
  input [71:0] DU;
  output reg [71:0] DC;
  output reg NOERROR, UCERR;
  integer syndrome [0:255];
  
  reg [71:0] C [1:8];    // Constants for parity-check matrix
  integer b, e, i, col;
  reg [7:0] syn;
  reg [7:0] SYND;

initial begin
  C[1] = 72'h80000000000000007f; C[2] = 72'h400000003fffffff80;
  C[3] = 72'h20001fffc0007fff80; C[4] = 72'h100fe03fc07f807f80;
  C[5] = 72'h0871e3c3c78787878f; C[6] = 72'h04b66cccd9999999b3;
  C[7] = 72'h02dab5556aaaaaaad5; C[8] = 72'hffffffffffffffffff;
  for (i=0; i<=255; i=i+1) syndrome[i] = -1; // Initialize syndrome array to invalid
  for (col=0; col<=71; col=col+1) begin // Populate valid syndromes
    for (e=1; e<=8; e=e+1) syn[8-e] = C[e][col];
    syndrome[syn] = col;
  end
end

always @ (DU) begin
  DC = DU;
  for (b=0; b<=7; b=b+1) SYND[b] = ^(C[8-b] & DU);  // Calculate received syndrome
    NOERROR = 1'b1; UCERR = 1'b0;         // Default values, no errors
    if (SYND[7:0]==8'b0) ;                                                     // No errors
    else if (syndrome[SYND]<0) begin NOERROR = 1'b0; UCERR = 1'b1; end         // Uncorrectable
    else if (SYND[0]!=1'b1) begin NOERROR = 1'b0; UCERR = 1'b1; end            // Uncorrectable
    else begin NOERROR = 1'b0;  DC[syndrome[SYND]] = ~DU[syndrome[SYND]]; end  // Correctable
  end
endmodule

*附件：ham.zip