求指教，哪位高手帮我看看这段跑表的verilog代码有什么问？

通信

module paobiao (CLK,CLR,PAUSE,Dout,Lout);
input CLK,CLR,PAUSE ;
output [6:0]Lout ;
output[5:0]Dout;
reg [6:0]Lout ;
reg[5:0]Dout;
reg [2:0]count ;
reg cn1,cn2;
reg [3:0] MSH,MSL,SH,SL,MH,ML;
wire[6:0] LED7S1,LED7S2,LED7S3,LED7S4, LED7S5,LED7S6;
DECL7S u1(.A(MSL[3:0]) ,.LED7S(LED7S1));//调用数码管译码模块
DECL7S u2(.A(MSH[3:0]) ,.LED7S(LED7S2));
DECL7S u3(.A(SL[3:0]) , .LED7S(LED7S3));
DECL7S u4(.A(SH[3:0]) , .LED7S(LED7S4));
DECL7S u5(.A(ML[3:0]) , .LED7S(LED7S5));
DECL7S u6(.A(MH[3:0]) , .LED7S(LED7S6));
//百分秒计数，满100进位
always @(posedge CLK or posedge CLR)
begin
if(CLR) begin //异步复位
{MSH,MSL}<=8'h00;
cn1<=0;
end
else if(!PAUSE) //PAUSE为0时正常计数，为1时暂停计数
begin //低位和高位满9时进位置零
if(MSL==9)
begin
MSL<=0;
if(MSH==9)
begin MSH<=0;
cn1<=1;
end
else MSH<=MSH+4'b0001;
end
else begin
MSL<=MSL+4'b0001; cn1<=0;
end
end
end
//秒计数进程，每计满60，cn2产生一个进位
always @(posedge cn1 or posedge CLR)
begin
if(CLR) begin //异步复位
{SH,SL}<=8'h00;
cn2<=0;
end
else if(SL==9) //低位是否为9
begin
SL<=0;
if(SH==5) begin SH<=0; cn2<=1; end
else SH<=SH+4'b0001;
end
else
begin SL<=SL+4'b0001; cn2<=0; end
end
//分钟计数进程，每计满60，系统自动清零
always @(posedge cn2 or posedge CLR)
begin
if(CLR)
begin {MH,ML}<=8'h00; end //异步复位
else if(ML==9) begin
ML<=0;
if(MH==5) MH<=0;
else MH<=MH+4'b0001;
end
else ML<=ML+4'b0001;
end
always@(posedge CLK or posedge CLR )
begin //选通信号
if(CLR)
count<=3'b000;
else if(count==3'b101)
count<=3'b000;
else
count<=count+3'b001;
end
always@(posedge CLK)
begin //数码管选通（共阴）
case(count)
3'b000:Dout<=6'b111110; //管1选通
3'b001:Dout<=6'b111101;
3'b010:Dout<=6'b111011;
3'b011:Dout<=6'b110111; //管4选通
3'b100:Dout<=6'b101111;
3'b101:Dout<=6'b011111;
endcase
end
always@(posedge CLK)
begin // 数据选通
case (count)
3'b000:Lout<=LED7S1; // 显示MSL
3'b001:Lout<=LED7S2;
3'b010:Lout<=LED7S3; // 显示SL
3'b011:Lout<=LED7S4;
3'b100:Lout<=LED7S5; // 显示ML
3'b101:Lout<=LED7S6;
endcase
end
endmodule
module DECL7S (A, LED7S); //数码管译码模块
input [3:0] A;
output [6:0] LED7S;
reg [6:0] LED7S;
always @(A)
begin
case(A)
4'b0000: LED7S <= 7'b0111111;
4'b0001: LED7S <= 7'b0000110;
4'b0010: LED7S <= 7'b1011011;
4'b0011: LED7S <= 7'b1001111;
4'b0100: LED7S <= 7'b1100110;
4'b0101: LED7S <= 7'b1101101;
4'b0110: LED7S <= 7'b1111101;
4'b0111: LED7S <= 7'b0000111;
4'b1000: LED7S <= 7'b1111111;
4'b1001: LED7S <= 7'b1101111;
default: LED7S <= 7'bx;
endcase
end
endmodule

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2012-5-30 11:36:53

还是自己去慢慢仿真调试吧

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求指教，哪位高手帮我看看这段跑表的verilog代码有什么问？

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