STM32H7作为SPI主机给FPGA发送数据出错是何原因

可以在drv_spi.c中先看下接口的具体实现，有没有对HAL部分存在使用错误的情况。

sck脉冲数量不对，还有许多毛刺，感觉像是引脚使用有冲突，其它地方也操作了sck的gpio引脚

那些不是毛刺，是波形图被压缩得太厉害了，所以看起来像。其实图里有48bits的数据传输，我没展开。

H7的spi驱动初始化函数, 看看是否有差异:

static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)

{

    RT_ASSERT(spi_drv != RT_NULL);

    RT_ASSERT(cfg != RT_NULL);

    SPI_HandleTypeDef *spi_handle = &spi_drv->handle;

    if (cfg->mode & RT_SPI_SLAVE)

    {

        spi_handle->Init.Mode = SPI_MODE_SLAVE;

    }

    else

    {

        spi_handle->Init.Mode = SPI_MODE_MASTER;

    }

    if (cfg->mode & RT_SPI_3WIRE)

    {

        spi_handle->Init.Direction = SPI_DIRECTION_1LINE;

    }

    else

    {

        spi_handle->Init.Direction = SPI_DIRECTION_2LINES;

    }

    if (cfg->data_width == 8)

    {

        spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;

        spi_handle->TxXferSize = 8;

        spi_handle->RxXferSize = 8;

    }

    else if (cfg->data_width == 16)

    {

        spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;

    }

    else

    {

        return RT_EIO;

    }

    if (cfg->mode & RT_SPI_CPHA)

    {

        spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;

    }

    else

    {

        spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;

    }

    if (cfg->mode & RT_SPI_CPOL)

    {

        spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;

    }

    else

    {

        spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;

    }

    if (cfg->mode & RT_SPI_NO_CS)

    {

        spi_handle->Init.NSS = SPI_NSS_SOFT;

    }

    else

    {

        spi_handle->Init.NSS = SPI_NSS_SOFT;

    }

    uint32_t SPI_APB_CLOCK;

#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)

    SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();

#elif defined(SOC_SERIES_STM32H7)

    SPI_APB_CLOCK = HAL_RCC_GetSysClockFreq();

#else

    SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();

#endif

    if (cfg->max_hz >= SPI_APB_CLOCK / 2)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 4)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 8)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 16)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 32)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 64)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;

    }

    else if (cfg->max_hz >= SPI_APB_CLOCK / 128)

    {

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;

    }

    else

    {

        /*  min prescaler 256 */

        spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;

    }

    LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",

          HAL_RCC_GetSysClockFreq(),

          SPI_APB_CLOCK,

          cfg->max_hz,

          spi_handle->Init.BaudRatePrescaler);

    if (cfg->mode & RT_SPI_MSB)

    {

        spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;

    }

    else

    {

        spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;

    }

    spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;

    spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

    spi_handle->State = HAL_SPI_STATE_RESET;

#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)

    spi_handle->Init.NSSPMode          = SPI_NSS_PULSE_DISABLE;

#elif defined(SOC_SERIES_STM32H7)

    spi_handle->Init.Mode                       = SPI_MODE_MASTER;

    spi_handle->Init.NSS                        = SPI_NSS_SOFT;

    spi_handle->Init.NSSPMode                   = SPI_NSS_PULSE_DISABLE;

    spi_handle->Init.NSSPolarity                = SPI_NSS_POLARITY_LOW;

    spi_handle->Init.CRCPolynomial              = 7;

    spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

    spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

    spi_handle->Init.MasterSSIdleness           = SPI_MASTER_SS_IDLENESS_00CYCLE;

    spi_handle->Init.MasterInterDataIdleness    = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;

    spi_handle->Init.MasterReceiverAutoSusp     = SPI_MASTER_RX_AUTOSUSP_DISABLE;

    spi_handle->Init.MasterKeepIOState          = SPI_MASTER_KEEP_IO_STATE_ENABLE;

    spi_handle->Init.IOSwap                     = SPI_IO_SWAP_DISABLE;

    spi_handle->Init.FifoThreshold              = SPI_FIFO_THRESHOLD_01DATA;

#endif

    if (HAL_SPI_Init(spi_handle) != HAL_OK)

    {

        return RT_EIO;

    }

#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)

        || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)

    SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);

#endif

    /* DMA configuration */

    if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)

    {

        HAL_DMA_Init(&spi_drv->dma.handle_rx);

        __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);

        /* NVIC configuration for DMA transfer complete interrupt */

        HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);

        HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);

    }

    if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)

    {

        HAL_DMA_Init(&spi_drv->dma.handle_tx);

        __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);

        /* NVIC configuration for DMA transfer complete interrupt */

        HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);

        HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);

    }

    __HAL_SPI_ENABLE(spi_handle);

    LOG_D("%s init done", spi_drv->config->bus_name);

    return RT_EOK;

}