上述模块的VHDL语言描述为:
library ieee;
use ieee.std_logic_1164.all;
entity RegDup is
port(
clk:in std_logic;
Dup:out std_logic_vector(6 downto 0);
M1:in std_logic);
end RegDup;
architecture rtl of RegDup is
begin
process(Clk)
begin
if Clk'event and Clk='1'then --系统时钟采样
Dup(0)<=M1; --复制M1信号
Dup(1)<=M1;
Dup(2)<=M1;
Dup(3)<=M1;
Dup(4)<=M1;
Dup(5)<=M1;
Dup(6)<=M1;
end if;
end process;
end rtl;