使用Quartus II 的浮点运算IP核，实现对一个未知二进制数除5

附上代码，已经仿真验证，可以实现，请问还有其它更简单的方法吗？


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-- use Division  IP  core achieve /5
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Division_ip is
port (
  Clk_i       :  in std_logic;
  Rst_i       :  in std_logic;
  DivisionA_i      :  in std_logic_vector(17 downto 0);
  DivisionC_o          : out std_logic_vector(17 downto 0)
);
end Division_ip;
architecture arch_Division_ip of Division_ip is
component M_Division port (
  clock       : IN  STD_LOGIC      ;
  dataa       : IN  STD_LOGIC_VECTOR (31 DOWNTO 0) ;
  datab       : IN  STD_LOGIC_VECTOR (31 DOWNTO 0) ;
  result       : OUT  STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

constant DivisionB_c     : std_logic_vector(31 downto 0) := b"0100_0000_1010_0000_0000_0000_0000_0000";
signal zero      : std_logic_vector(31 downto 0) := b"0000_0000_0000_0000_0000_0000_0000_0000";
shared variable  i     : integer range 0 to 17;
signal  j       : integer range 0 to 256;
signal Dataa_s      : std_logic_vector(31 downto 0);
signal DivisionA_s     : bit_vector(17 downto 0);
signal  DivisionD_s     : bit_vector(31 downto 0);
signal DivisionC_s     : std_logic_vector(23 downto 0);
signal result_s     : std_logic_vector(31 downto 0);

begin
DivisionA_s <= to_bitvector(DivisionA_i);

process (Rst_i, Clk_i) begin
  if (Rst_i = '0') then
   i := 17;
   Dataa_s <= (others => '0');
  elsif rising_edge (Clk_i) then
   if (DivisionA_i(i) = '1') then
    Dataa_s(22 downto 5 ) <=to_stdlogicvector( DivisionA_s SLL (18-i));
    Dataa_s(30 downto 23) <= conv_std_logic_vector(i+127,8);
   else
    i := i - 1;
   end if;
  end if;
end process;

process (Rst_i, Clk_i) begin
  if (Rst_i = '0') then
   DivisionC_s <= (others => '0');
  elsif rising_edge (Clk_i) then
   DivisionC_s <= to_stdlogicvector( ('1' & DivisionD_s(22 downto 0)) SRL (150 - j));
  end if;
end process;

j <= conv_integer(result_s(30 downto 23));
DivisionD_s <= to_bitvector(result_s);

U_M_Division_0 : M_Division port map (
  clock       => Clk_i        ,
  dataa       => Dataa_s        ,
  datab       => DivisionB_c       ,
  result       => result_s
);

DivisionC_o <= DivisionC_s(17 downto 0);

end arch_Division_ip;