TAS5731M+CS5340数字功放无法工作该怎么办？

大家好，我是个新手，现在在做一个数字音频功放项目，模拟音频信号输入CS5340转换成24位的数字信号经过I2S送给TAS5731M，TAS5731M配置成PBTL模式，输出至喇叭，滤波频率设置成20Hz到100Hz。原理图已经画好做出样板了，但CS5340和TAS5731M的文档我翻了好几遍，发现它们都不能提供MCLK，现在的图上两边的主时钟就是直接连上的，开始以为是作主机的CS5340会提供主时钟的，结果好像不是这样。

以下是找的网上的初始化参数设置，现在板子一点反应也没有，怎么也工作不了，请各位大神帮忙看一看。
首先硬件上是不是还需要一个提供一个外部MCLK给这两个芯片的I2S用，再有就是下面这个初始化程序还有哪些地方不对。
void tas_PUP(void)
[
const uint8_t out_MuxReg[4] = [0x01,0x00,0x22,0x45]; //addr = 0x25,ti ?§3?é???
const uint8_t in_MuxReg[4] = [0x00,0x99,0x77,0x72]; //addr = 0x20,BD mode,select R_CH to PBTL
uint8_t i;

// code uint8_t out_MuxReg[4] = [0x01,0x01,0x23,0x45]; //addr = 0x25,TI ???????t
// code uint8_t out_MuxReg[4] = [0x01,0x10,0x32,0x45]; //addr = 0x25,datasheet pag25
// code uint8_t in_MuxReg[4] = [0X00,0X88,0X77,0X72]; //addr = 0x20,BD mode,select L_CH to PBTL
tas_nRST = 0;
RST_5340 = 0;
M0_5340 = 0;
M1_5340 = 0;
tas_delay(1000);

tas_nRST = 1;
RST_5340 = 1;

tas_delay(1000);
sendbuf[0] = 0x00;
writeNbyte(0x1b,1); //Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms
//PutStr("Trim oscillatorn");
tas_delay(2000);
/****************Configure the DAP via I2C****************/
sendbuf[0] = 0x80;
writeNbyte(0x03,1); //sys ctrl reg 1;Soft unmute on recovery from clock error
//tas_WrByte(0X05,0x04); //éè??I2Sêy?Y??ê?￡?24bit I2S PHLIP mode
//tas_WrByte(0X30,0x07); //éè??master volume for 0dB
sendbuf[0] = 0x30;
writeNbyte(0x07,1);

sendbuf[0] = 0xB8;
writeNbyte(0x11,1); //for BD mode , if chg to AD mode,need chg the conf
sendbuf[0] = 0x60;
writeNbyte(0x12,1); //for BD mode,System ??è??aAD?￡ê?
sendbuf[0] = 0xA0;
writeNbyte(0x13,1); //for BD mode
sendbuf[0] = 0x48;
writeNbyte(0x14,1); //for BD mode

for(i=0;i<4;i++)
[
sendbuf = in_MuxReg;
]
writeNbyte(0x20,4);

for(i=0;i<4;i++)
[
sendbuf = out_MuxReg;
]
writeNbyte(0x25,4);
sendbuf[0] = 0x3A;
writeNbyte(0x19,1); //for PBTL mode
/*********************Exit shutdown***********************/
sendbuf[0] = 0x00; //0x02
writeNbyte(0x05,1); //exit shutdown command may not be serviced for as much as 240 ms
//after trim following AVDD/DVDD power-up ramp
//ADR/FAULT pin is configured as fault output
tas_delay(2000);
//tas_WrByte(0X30,0x07);//éè??master volume for 0dB
//tas_WrByte(0Xc0,0x08);//éè?? CH1 ò?á?
]