如何用4个时钟检测窄脉冲

mananshah93写道：
从根本上有什么不对吗？
是的，很多东西。
首先，这个：
过程（clk0） 
if（myclk ='1'和clk0 ='1'）然后 - 其中myclk  - >输入引脚和clk0-> 4 Mhz时钟，0度相移qdata0输入脉冲计数器...结束if;结束过程;
是一个组合过程;
它对没有时钟边缘很敏感。
接下来，您试图在250 ns时钟的四个边沿之一上捕获16 ns脉冲（上升和下降时间为8 ns？真的？），也就是说，粒度为62.5 ns。
为什么你认为这会有用？
----------------------------是的，我这样做是为了谋生。



以下为原文

mananshah93 wrote: 
Is there anything wrong fundamentally?

Yes, lots of things.
 
First, this:
 
process (clk0)
    if (myclk = '1' and clk0 = '1') then   -- where myclk -> input pin and clk0-> 4 Mhz clock with 0 degree phase shift
        qdata0 <= qdata0 + "00000001";  qdata-> Counter for input pulse...
   end if;
end process;
 
is a combinatorial process; it is sensitive to no clock edge.
 
Next, you're trying to capture a 16 ns pulse (with 8 ns rise and fall times? really?) on one of four edges of a 250 ns clock, that is to say with 62.5 ns granularity. Why do you think that will ever work?
----------------------------Yes, I do this for a living.

谢谢贝斯曼......
好的......让我简单解释一下我的逻辑......假设我有一个20ns脉冲宽度和8ns上升/下降时间的输入脉冲......（目前这是我有的最短时间源，我想要
比这更小..）我有4个时钟相互90度相移，可能的最大频率和25％的导通时间....这4个时钟连续采样输入脉冲...所以，当输入
脉冲冲击...理想情况下，它应该只能被4个时钟中的一个检测到......或者是罕见的两个......
所以，我使用DCM生成了4个时钟...但我怀疑它是否真的改变了......我在ip core中取消选中相位对齐复选框...
“上一篇文章中的代码不正确”......我试过这部分成功...
过程开始
如果rising_edge（clk0）然后--clk0  -  0度相移时钟...如果（myclk ='1'）那么 -  myclk ---输入引脚用于脉冲qdata0结束if;
结束如果;结束过程;
其他时钟的过程也一样.....告诉我实现这个或其他什么的错误....
再次感谢...



以下为原文

Thanks bassman...
 
Ok... Let me explain my logic in brief......  Let say I have a input pulse with 20ns pulse width and 8ns rise/fall time...(currently this is least time period source I have, I want less than this.. )  I have 4 clocks with 90 degree phase shift from each other with maximum frequency possible and 25% on-time.... These 4 clocks are sampling continuosly for the input pulse... So, when a input pulse strikes... ideally it should be detected by only one of the 4 clocks... or two in rare occurence.....
So, I have generated 4 clocks using DCM... but I doubt if it really shifts or not... I have unchecked phase align check box in ip core...
 
" The code was incorrect in previous post"... I have tried this with partial success... 
 
process
begin
if rising_edge(clk0) then    -- clk0 -- 0 degree phase shift clock...
if (myclk = '1') then               -- myclk --- input pin for pulse
qdata0 <= qdata0 + "00000001"; -- counter
end if;
end if;
end process;
 
Same process for other clocks too..... Tell me if some error in implementing this or anything else....
 
Thanks again...
 

对不起，我忘了添加一件事......
最重要的是我需要识别脉冲到达的单个时钟....我的意思是在4个时钟的特定时钟的时间内应该检测到脉冲的上升沿....任何建议如何
要做到这一点？
谢谢，



以下为原文

I am sorry, I forgot to add one thing...
 
The most important thing is that I need to identify a single clock during which pulse has arrived.... I mean during on time of a particular clock out of 4 clocks rising edge of the pulse should be detected.... Any suggestion how to do that?
 
Thanks,
 

mananshah93写道：
谢谢贝斯曼......
好的......让我简单解释一下我的逻辑......假设我有一个20ns脉冲宽度和8ns上升/下降时间的输入脉冲......（目前这是我有的最短时间源，我想要
比这更小..）我有4个时钟相互90度相移，可能的最大频率和25％的导通时间....这4个时钟连续采样输入脉冲...所以，当输入
脉冲冲击...理想情况下，它应该只能被4个时钟中的一个检测到......或者是罕见的两个......
这一切都很好，但它假设采样时钟频率高于输入信号频率。
在您的第一篇文章中，您说您正在生成4 MHz（250 ns周期）的采样时钟，并且您无法使用该时钟捕获20 ns脉冲！
----------------------------是的，我这样做是为了谋生。



以下为原文

mananshah93 wrote:
Thanks bassman...
 
Ok... Let me explain my logic in brief......  Let say I have a input pulse with 20ns pulse width and 8ns rise/fall time...(currently this is least time period source I have, I want less than this.. )  I have 4 clocks with 90 degree phase shift from each other with maximum frequency possible and 25% on-time.... These 4 clocks are sampling continuosly for the input pulse... So, when a input pulse strikes... ideally it should be detected by only one of the 4 clocks... or two in rare occurence.....
 

That is all well and good, but it assumes that the sampling clock frequency is higher than the input signal frequency.
 
In your first post, you said that you were generating a sample clock at 4 MHz (250 ns period) and there's no way you'll be able to capture a 20 ns pulse with that clock!
----------------------------Yes, I do this for a living.

再次感谢...你是对的，实际上我想要频率超过那个...但是当我增加到100MHz然后所有时钟都检测到脉冲...我想时钟为375 MHz ...我的意思是高
尽可能...但是无法区分时钟，因为所有4个都检测到......有可能吗？



以下为原文

Thanks again... You are right, actually I want frequency more than that... But when I increase to 100MHz then all clock detect the pulse... I would like to clock to be 375 MHz... I mean as high as possible... But not able to discriminate among clocks as all 4 detects... Is it possible?

mananshah93写道：再次感谢...你是对的，实际上我想要频率超过那个...但是当我增加到100MHz然后所有时钟检测到脉冲...我想时钟为375 MHz ...我
意味着尽可能高......但是不能区分时钟，因为所有4个都检测到......有可能吗？
您要做的是检测四相中的每一相何时看到输入脉冲的EDGE。
这很容易做到。
----------------------------是的，我这样做是为了谋生。



以下为原文

mananshah93 wrote:
Thanks again... You are right, actually I want frequency more than that... But when I increase to 100MHz then all clock detect the pulse... I would like to clock to be 375 MHz... I mean as high as possible... But not able to discriminate among clocks as all 4 detects... Is it possible?

What you want to do is to detect when each of your four phases sees the EDGE of the input pulse. That's fairly easy to do.
----------------------------Yes, I do this for a living.

“你想要做的是检测四个阶段中每个阶段何时看到输入脉冲的边缘。这很容易做到。”
不完全......但只有一个时钟是第一个看到输入....
是的......我尝试但是我得到的是每当输入到达时......所有四个时钟都检测到它......所以，将clcok时间段分成四个部分的目的并不能解决....我只是想要
找到实际检测输入边缘的第一个时钟....
尝试了几种方法......但我想错过了什么......有什么建议吗？
再次感谢...



以下为原文

"What you want to do is to detect when each of your four phases sees the EDGE of the input pulse. That's fairly easy to do."
Not exactly... but only one clock which is first to see input....
 
Yes... I tried but what I am getting is that the whenever the input is arrived... all four clocks detects it...So, purpose of dividing the clcok period into four parts doesnot solve....I just want to find the first clock which actually detects the edge of input ....
Tried several ways... but missing something I guess... Any suggestion?
 
Thanks again...

mananshah93写道：
“你想要做的是检测四个阶段中每个阶段何时看到输入脉冲的边缘。这很容易做到。”
不完全......但只有一个时钟是第一个看到输入....
是的......我尝试但是我得到的是每当输入到达时......所有四个时钟都检测到它......所以，将clcok时间段分成四个部分的目的并不能解决....我只是想要
找到实际检测输入边缘的第一个时钟....
尝试了几种方法......但我想错过了什么......有什么建议吗？
当然，当一个足够长的脉冲到来时，所有四个时钟相位最终都会看到它。
你关心的是哪个时钟相首先看到了脉冲边沿。
问题是你必须将这四个边沿从它们各自的时钟相位全部移动到一个时钟相位，然后才能确定你的逻辑首先确定哪一个。
查看XAPP225和XAPP225以获得可能的解决方案。
----------------------------是的，我这样做是为了谋生。



以下为原文

mananshah93 wrote:
"What you want to do is to detect when each of your four phases sees the EDGE of the input pulse. That's fairly easy to do."
Not exactly... but only one clock which is first to see input....
 
Yes... I tried but what I am getting is that the whenever the input is arrived... all four clocks detects it...So, purpose of dividing the clcok period into four parts doesnot solve....I just want to find the first clock which actually detects the edge of input ....
Tried several ways... but missing something I guess... Any suggestion?

Certainly, when a long-enough pulse arrives, all four clock phases will eventually see it. What you care about is which clock phase first saw the pulse edge. The thing is that you have to move those four edges from their individual clock phases all onto one clock phase, and only then can your logic really determine which came first.
 
Check out XAPP225 and XAPP225 for a possible solution.
----------------------------Yes, I do this for a living.

谢谢贝斯曼......
XAPP225似乎是可能的解决方案，我试图理解逻辑，有一点我需要问你，在图3（输入阶段）......第一阶段之后......哪些时钟用于采样区B，C和D
....我对此感到困惑....似乎所有区域的第一阶段都没有相同的时钟.....
谢谢...
xapp225.pdf 153 KB



以下为原文

Thanks bassman......
 
XAPP225 seems to be possible solution, I was trying to understand logic, one thing I need to ask you that in figure 3 (input stage)... after first stage... which clocks are used for sampling zone B,C and D.... I am little confused about that.... It doesn't seem that same clocks used for first stage for all zones respectively.....
 
Thanks...
            xapp225.pdf ‏153 KB