为什么我的代码不起作用？

不知道为什么我不能编辑我的原帖，很抱歉双帖。
这是我在自述文件中找到的问卷...
1.阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？
- 是的，我已将其下载并多次转向它。
2.搜索论坛（并搜索网页）以查找类似主题。
- 搜索不会导致任何符合我指定问题的答案，或者没有提供与我自己相关的解决方案。
6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）。
- 如果需要任何其他信息，请索取。
我将非常乐意提供其他代码或资源来帮助解决我的问题。



以下为原文

Not sure why I cannot edit my original post, so sorry for the double post. Here is the questionaire I found in the Read Me thread...
 
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
- Yes, I have it downloaded and have turned to it numerous times.

2. Search the forums (and search the web) for similar topics.
- Searches did not result in any answers fitting my specified problem or did not provide resolution in terms relating to my own.
 
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
- If any additional information is required please ask for it. I will be more than happy to provide additional code or resources to help resolve my issue.
 

justinmcgillivary写道：
大家好！
我在Verilog的代码和编程方面遇到了一些麻烦。
我有几本书，几本教程和所有推荐的材料，其中包括其他东西。
然而，由于缺乏ISE软件传播的勘误定义，我对此感到非常恼火。
这意味着我只是在我的代码中试用了一切。
这是我提供的Full Adder代码。
//制作一个4位全加器
模块Full_Adder
（
//创建输入A x 4
输入[3：0] A，
//创建输入B x4
输入[3：0] B，
//创建输出@ 8位宽（仅需4 +进位，但我使用8）
输出[7：0] LED
）;
//创建寄存器以存储Sum的值
reg [7：0]总和;
//定义Sum的作用...... 
Sum = A + B;
//使输出等于总和
分配LED = Sum;
endmodule
我得到的勘误是......
[引用]
错误：HDLCompilers：26  - “Full_Adder.v”第31行意外令牌：'='错误：HDLCompilers：26  - “Full_Adder.v”第31行意外令牌：'+'ERROR：HDLCompilers：26  - “Full_Adder.v”行
31个意外的令牌：';'
[/引用]
当然，很明显发现了一个“意外的令牌”，但为什么！？不知道错误的原因或原因并没有帮助我解决错误。
欢迎来到Verilog，这是一种......愚蠢的语言。
无论如何。
回答有关“你为什么会遇到这些错误”的问题。
您已将信号Sum声明为reg，但您将其用作连续分配的目标。
那不是合法的Verilog。
如果您将信号声明为reg，则必须在always块中指定它，例如 
总是@（a或b） 
Sum = A + B;
（请注意，此块对任何边缘都不敏感，因为您正在描述组合块。）
无论出于何种原因，解析器都会给你一个错误的错误消息。
我很惊讶它并没有说出来，“reg类型信号必须在一个始终的块中分配。”
因此解析器会对Sum赋值进行阻塞并保持混淆，因此它无法解析行的其余部分，从而导致错误。
或者，您可以简单地将Sum声明为连线并保持连续分配。
实际上，您可以简单地消除间隙信号Sum并直接分配给LED。
最后，查看Verilog-2001端口定义，因为您可以声明端口信号的方向（输入，输出）及其类型（wire，reg），而无需分离类型（reg）声明。
最后，Austin声称“FPGA器件需要同步设计......意味着时钟。”
嗯，在大多数情况下，当然对于任何复杂的任何真实设计，这都是真的。
但是，出于学习和演示的目的，您的加法器不需要注册或使用时钟。
因此，尽管他的意图是好的，但他在帖子中所说的内容实际上并没有解决你的问题。
请记住，在Verilog中，reg并不意味着需要同步描述。
这只是一种不幸的选择。
所有reg意味着，如上所述，它必须在always块中分配。
总是块不必描述同步逻辑！
----------------------------是的，我这样做是为了谋生。



以下为原文

justinmcgillivary wrote:
Hello all! I am having some troubles with my code and programming in Verilog altogether. I have a few books, several tutorials and all the recommended material from the stickies among other things. However I am getting very irritated with the lack of definitions of the errata that is propogated by the ISE software. This means that I am just trial-and-error'ing everything in my code. Here is my provided code for a Full Adder.
 
// Make an 4 bit Full Addermodule Full_Adder(// Create Input A x 4input [3:0] A,// Create Input B x4input [3:0] B,// Create Output @ 8-bits wide (only need 4 + carryout, but I used 8)output [7:0] LED);// Create register to store the value of Sumreg [7:0] Sum;// Define what Sum does... Sum = A + B;// Make the Outputs equal to the Sumassign LED = Sum;endmodule 
The errata I get is...
 

ERROR:HDLCompilers:26 - "Full_Adder.v" line 31 unexpected token: '='
ERROR:HDLCompilers:26 - "Full_Adder.v" line 31 unexpected token: '+'
ERROR:HDLCompilers:26 - "Full_Adder.v" line 31 unexpected token: ';'

 
Granted it's obvious an 'unexpected token' was found, but WHY!? Not knowing how or why the error is there doesn't help me in solving the errors.
 

Welcome to Verilog, a language which is .... daft.
 
ANYWAYS. To answer the question about "why are you getting these errors."
 
You've declared the signal Sum as a reg, but you use it as the target of a continous assignment. That's not legal Verilog. 
 
If you declare a signal as a reg, you must assign to it in an always block, something like
 
   always @(a or b)
       Sum = A + B;
 
(Note that this block is not sensitive to any edges, because you're describing a combinatorial block.)
 And for whatever reason, the parser is giving you a dopey error message. I'm surprised that it didn't come right out and say, "reg type signals must be assigned in an always block." So the parser chokes on the Sum assignment and remains confused so it can't parse the rest of the line, hence the error.
  Alternatively, you could simply declare Sum as a wire and leave the continuous assignment as is. Actually, you could simply eliminate the interstitial signal Sum and assign directly to LED.
 
Finally, look into the Verilog-2001 port definitions, since you can declare the port signal's direction (input, output) as well as its type (wire, reg) without having to separate out the type (reg) declarations.
 
 
Finally, Austin claims that "FPGA devices require synchronous designs ... implies a clock."  Well, for the most part, and certainly for any real design of any complexity, that's true.
 
But your adder, for purposes of learning and demonstration, doesn't need to be registered or to use a clock. So while his intentions are good, what he says in his post doesn't actually address your question.
 
Remember that in Verilog, reg does NOT imply the need for a synchronous description. It's just an unfortunate choice of type. All that reg means is that, as noted above, it must be assigned in an always block. And always blocks do not have to describe synchronous logic!
----------------------------Yes, I do this for a living.

感谢一大堆澄清为什么它给了我这个错误！
非常感激！
这个错误......
错误：HDLC编译器：26  - “Full_Adder.v”第8行期待'endmodule'，找到'else'
我无法解释。
我有时候工作，其他人不是真的不知道为什么有时候我会得到这个错误，而有时我不知道。
我查看的所有语法都表明我的代码应该是正确的。
代码是......
模块触发器（a，b，LED）;
//定义I / O.
输入a;
输入b;
//使用REG为LED存储逻辑值1或0
输出reg LED;
//每当clk（b）变高时，检查a是否高...
总是@（posedge b）开始
b
LED
我决定通过使用较小的代码来帮助正确理解错误一直出现的原因来解决问题。
根据我输入的内容，我看不出它在给定的行上是如何找到'endmodule'的（突出显示粗体加上更大的字体）。
为什么它假设它应该找到一个与任何其他类型的代码相反的endmodule？
这个让我感到困惑。
哈哈



以下为原文

Thanks a bunch for clarifying why it gave me that error! Much appreciated! This error...
 
ERROR:HDLCompilers:26 - "Full_Adder.v" line 8 expecting 'endmodule', found 'else'
 
I cannot explain. 
 
I've had it work sometimes and others not without really knowing the difference of why sometimes I get this error and other times I do not. All the syntax I have reviewed has indicated that my code should be correct. The code is...
 
module flipflop (a, b, LED);// Define I/O'sinput a;input b;// Use REG to store logical value of 1 or 0 for the LEDoutput reg LED;// Any time the clk (b) goes high, check if a is high...always @ (posedge b) beginb <= 1;// If both are a and b are high, LED is highend else if (a and b) beginLED <= 1;endendmodule  
 
I decided to troubleshoot the issue by using smaller pieces of code to help correctly understand why the error is consistently showing up. From what I have typed I do not see how it expected to find an 'endmodule' at the given line (highlighted bold plus larger font). Why is it assuming it should find an endmodule there as oppossed to any other type of code? This one has me perplexed. haha

看起来你需要一本更好的书......
Verilog是一种硬件描述语言（HDL）。
这意味着它是一种编程语言，带有一些“额外”的东西，可以用来描述硬件。
使用Verilog，就像使用任何语言一样，可以编写和模拟任何语法上合法的东西。
但是，当您进行综合时，综合的目标是将函数的行为描述映射到真实硬件资源（即FPGA内的资源）。
只有在使用寄存器传输语言（RTL）样式编码HDL时才能执行此操作。
RTL中的编码（因此，可综合编码）是Verilog语言可以做的一小部分。
那么让我们来看看可以合成的东西。
在FPGA中，有两种资源 - 组合逻辑和触发器（也有锁存器，但我会忽略它们，因为你不应该考虑它们）。
触发器是在某个信号（时钟）的上升沿更新其数据输出的单元。
这是触发器的基本描述。
在Verilog中，我们需要使用描述此行为的代码对此进行编码
总是@（posedge clock）
开始 
结束
这与触发器的描述相匹配 - 它的值仅在时钟的上升沿改变。
现在让我们来看看组合逻辑。
什么时候更新？
考虑一个真正的AND门 - 只要其输入发生任何变化，其输出就会发生变化。
因此，要在Verilog中对其进行编码，行为代码必须与功能相匹配
总是@（a或b） 
AND_OUT = a＆amp;＆amp;
b;
// AND_OUT是一个注册表
要么
总是@（*） 
AND_OUT = a＆amp;＆amp;
b;
// AND_OUT是一个注册表
要么
分配AND_OUT = a＆amp;＆amp;
b;
// AND_OUT是一根电线
你所写的不是这些，因此是不可综合的。
为了让所有这一切都有意义，你需要 
a）理解（至少一些）语言Verilog 
b）清楚地了解您要在硬件方面描述的功能 
c）描述与此硬件描述一致的行为
Avrum



以下为原文

It kindof looks like you are going to need a better book...
 
Verilog is a Hardware Description Language (HDL). What this means is that it is a programming language with some "extra" stuff to allow for the description of hardware. Using Verilog, just like using any language, anything that is syntactically legal can be written and simulated.
 
However, when you get to synthesis, the goal of synthesis is to map a behavioral description of a function to a real hardware resource (i.e. a resource within the FPGA). This can only be done when the HDL is coded using Register Transfer Language (RTL) style. Coding in RTL (thus, synthesizable coding) is a small-ish subset of what the Verilog language can do.
 
So lets look at what can be synthesized. In the FPGA, there are two kinds of resources - combinatorial logic and flip-flops (there are also latches, but I am going to ignore them since you should't be considering them).
 
A flip-flop is a cell that updates its data output on the rising edge of some signal (a clock). This is the fundamental description of a flip-flop. In Verilog, we need to code this using code that describes this behavior
 
always @(posedge clock)
begin
 
end
 
This matches the description of a flip-flop - its value changes only on the rising edge of the clock.
 
Now lets look at combinatorial logic. When does it update? Think about a real AND gate - its output changes whenever either of its inputs change. Thus to code for it in Verilog, the behavioral code must match the functionality
 
always @(a or b)
  AND_OUT = a && b;   // AND_OUT is a reg
 
or
 
always @(*)
   AND_OUT = a && b; // AND_OUT is a reg
 
or
 
assign AND_OUT = a && b; // AND_OUT is a wire
 
What you have written is none of these, and hence is not synthesizable.
 
In order for all of this to make sense you need to
  a) Understand (at least some of) Verilog, the language
  b) Have a clear understanding of the functionality of what you are trying to describe in terms of hardware
  c) Describe the behavior that is consistant with this hardware description
 
Avrum