没有用于存储器端口FIFO的驱动时钟信号

你好，
我刚刚开始使用与DDR3内存接口的MCB设计。
我已经配置并运行MIG工具来生成一个用于测试/模拟的示例设计。
我正在检查sim_tb_top.v测试平台文件及其模拟波形，以便更好地处理用户界面信号，但是我对设备_top.c3_p0_cmd_clk，design_top.c3_p0_wr_clk或ordesign_top.c3_p0_rd_clk缺少时钟转换感到困惑。
- 他们在整个模拟中都留在HiZ。
虽然我能够检查其他信号波形以供参考，但是看到没有用于存储器端口FIFO（cmd，wr和rd）的驱动时钟信号是令人困惑的。
有人可以帮忙解释一下吗？
谢谢，
德鲁



以下为原文

Hello,

I'm just getting started on a MCB design interfacing to a DDR3 memory. I've configured and run the MIG tool to generate an example design to test/simulate with. I'm examining the sim_tb_top.v testbench file and it's simulated waveforms in order to get a better handle of the user interface signals, but I'm confused by the lack of clock transitions on either design_top.c3_p0_cmd_clk, design_top.c3_p0_wr_clk, or design_top.c3_p0_rd_clk - they remain at HiZ the entire simulation.

While I'm able to inspect the other signal waveforms for reference, it is confusing to see no driving clock signals for the memory port FIFOs (cmd,wr, and rd). Can anyone help explain this?

Thank you,
Drew