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董事会是新的,但到目前为止并不是第一次使用Spartan3芯片,但它们都是由一个不再和我们在一起的人完成的,而且我是这方面的新手(我通常都会使用固件)。 现在这个很奇怪: - 我可以看到设备受影响(“获取设备ID”,“读取设备状态”) - “擦除”和“空白支票”也很好。 - “只编程FPGA”即可。 - “程序闪存和FPGA”可以很好地完成所有工作,除了提升DONE引脚,导致它失败。 - 当我进行“回读”时,它工作,DONE引脚变高 - >看起来DONE引脚工作,毕竟。 - DONE引脚上有一个LED,就像我们所有的设计一样,因此很容易看到。 - 如何将我读回的文件与位文件进行比较,看它们是否匹配? - 当我给电路板供电时,FPGA没有启动(再也没有)。 - 电力循环后我做了一次成功的“回读”,DONE变高了。 “我们从哪里开始......” - Alan Parsons Project。 这不是我的地盘,所以我可以使用任何我能得到的帮助...... 你的,Christian Treczoks B8编程问题.txt 6 KB 以上来自于谷歌翻译 以下为原文 Hi! The board is new, but by far not the first with Spartan3 chips here, but they were all done by a guy who is no longer with us, and I'm new to this aspect (I usully do the Firmware). Now this one is odd: - I can see the device on impact ("Get Device ID", "Read Device Status") - "Erase" and "Blank Check" is fine, too. - "Program FPGA Only" is OK. - "Program Flash and FPGA" does everything nicely, except raising the DONE pin, which causes it to fail. - When I do a "Readback", it works, and the DONE pin goes high -> Looks like the DONE pin works, after all. - There is an LED attached to the DONE pin, like in all our design, so it is easy to see. - How do I compare the file I read back to the bit file to see whether they match? - When I powercycle the board, the FPGA does not come up (no NONE, again). - I did a successful "Readback" after powercycling, DONE goes high. "Where do we go from here..." - Alan Parsons Project. This is not really my turf, so I can use any help I can get... Yours, Christian Treczoks B8 Programming Problem.txt 6 KB |
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检查模式引脚是否设置正确,以便从闪存中编程FPGA。如果您使用的是spartan-3AN FPGA并尝试从闪存进行配置,则检查“VS”引脚是否正确设置请参阅ug332以获取电路级详细信息以确认
硬件设置正确http://www.xilinx.com/support/documentation/user_guides/ug332.pdf -------------------------------------------------- ----------------------------别忘了回复,给予kudo并接受为解决方案--------- -------------------------------------------------- ------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Check if the mode pins are set correctly to program the FPGA from flash. If you are using spartan-3AN FPGA and trying to configure from flash..then check the "VS" pins are set correctly Refer to ug332 for the circuit level details to confirm the hardware is setup correctly http://www.xilinx.com/support/documentation/user_guides/ug332.pdf------------------------------------------------------------------------------ Don't forget to reply, give kudo and accept as solution ------------------------------------------------------------------------------View solution in original post |
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LED是直接连接到DONE线还是通过缓冲器?
----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 is the LED connected directly to the DONE line or through a buffer? ----------------------------Yes, I do this for a living. |
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检查模式引脚是否设置正确,以便从闪存中编程FPGA。如果您使用的是spartan-3AN FPGA并尝试从闪存进行配置,则检查“VS”引脚是否正确设置请参阅ug332以获取电路级详细信息以确认
硬件设置正确http://www.xilinx.com/support/documentation/user_guides/ug332.pdf -------------------------------------------------- ----------------------------别忘了回复,给予kudo并接受为解决方案--------- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Check if the mode pins are set correctly to program the FPGA from flash. If you are using spartan-3AN FPGA and trying to configure from flash..then check the "VS" pins are set correctly Refer to ug332 for the circuit level details to confirm the hardware is setup correctly http://www.xilinx.com/support/documentation/user_guides/ug332.pdf------------------------------------------------------------------------------ Don't forget to reply, give kudo and accept as solution ------------------------------------------------------------------------------ |
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> LED是直接连接到DONE线还是通过缓冲器?
就像在这里的所有其他设计(完美地工作)一样,它是这样完成的: 接地 - LED - 120R - 完成PIN - 1K8 - 3.3V 以上来自于谷歌翻译 以下为原文 > is the LED connected directly to the DONE line or through a buffer? Like in all the other designs here (which work perfectly), it is done like this: Ground - LED - 120R - DONE PIN - 1K8 - 3.3V |
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>检查模式引脚是否设置正确,以便从闪存中编程FPGA。
那是杯赛。 M0到M2用作输出,M2应该具有足够的下拉。 它现在有了,它的确有效! 非常感谢所有帮助过的人。 你的,Christian Treczoks 以上来自于谷歌翻译 以下为原文 > Check if the mode pins are set correctly to program the FPGA from flash. That was the cuprit. The M0 to M2 were used as outputs, and the M2 should have a sufficiant pulldown. It now has, and it works! Big thanks to everybody who helped. Yours, Christian Treczoks |
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