为什么在配置期间fpga引脚上会发生某些事情？

大家好，
我知道我使用的是过时的设备，但我希望能为我的问题找到一些帮助。
使用的设备是xc3s400。
在我的应用程序中，它连接到运行linux的cortex a8应用程序处理器的外部存储器总线。
保持根fs的nand也连接到该总线（其他芯片选择）。
如果我通过jtag（总线访问等）将其直接加载到FPGA中，我的设计已经可以工作了。
问题是，如果我将我的设计存储在prom（xcf02s）设备中，在配置期间，总线引脚上似乎会发生某些事情，导致linux引导加载程序失败。
HSWAP_EN正在浮动。
到目前为止我尝试的是：
- 使用简单的设计，将所有输出/输出引脚设置为“Z”高阻抗 - >相同的行为。
- 使用“STARTUP_SPARTAN3”原语将GTS线保持为高电平，超时时间足以让linux内核启动 - > samebehavior。
- 使用bitgen属性的启动选项“GTS_cycle = Keep”，似乎工作 - > linux能够启动，唯一的问题是我不知道如何再次启用引脚，一个定时器来清除STARTUP_SPARTAN3 GTS线路
不能像连接到STARTUP_SPARTAN3 GTS线路的输入引脚那样工作。
我的问题是为什么在配置期间fpga引脚上会发生某些事情，尽管它不应该以及如果我使用“GTS_cycle = Keep”该怎么办。
最好的问候
莱因哈德



以下为原文

Hello to everyone,

I know I'm using an outdated device, nevertheless I hope to get some help for my problem.
The used device is a xc3s400.
In my application it is connected to the external memory bus of an cortex a8 application processor running linux on it.
The nand which holds the root fs is also connected to this bus (other chip select).
My Design works already if I load it directly into the fpga over jtag (bus access, etc...). The problem is that if I store my design in the prom(xcf02s) device, something seems to happen on thebus pins during the configuration causing the linux boot loader to fail. HSWAP_EN is floating.

What I have tried so far is:
-Use a simple design which sets all out/inout pins to 'Z' high impedance -> same behavior.
-Use the "STARTUP_SPARTAN3" primitive to hold the GTS line high for a timeout large enough to let the linux kernel boot -> same behavior.
-Use the startup option of the bitgen properties "GTS_cycle=Keep", seems to work -> linux is able to boot, the only problem is that I'm not sure how to enable the pins again, a timer to clear the STARTUP_SPARTAN3 GTS line doesn't work as well as an input pin connected to STARTUP_SPARTAN3 GTS line.

My Questions are why is does something happens on the fpga pins during configuration although it shouldn't and what to do if I use  "GTS_cycle=Keep".

Best regard
Reinhard