将BIN转换为BCD显示问题

我有一个简单的8位输入二进制问题，bcd显示为7seg。
我得到最后一个数字显示正常，但前两个仍然是黑暗的。
例如，11111111的8位二进制输入应显示255，但我只能显示5。
我附上了我目前的代码。
我一开始以为这是时钟，但我无法弄明白。
以下是七段显示的代码：
实体x7seg是
港口（
x：在STD_LOGIC_VECTOR（15 downto 0）;
clk：在STD_LOGIC中;
clr：在STD_LOGIC中;
a_to_g：out STD_LOGIC_VECTOR（6 downto 0）;
an：out STD_LOGIC_VECTOR（3 downto 0）;
dp：输出STD_LOGIC
）;
结束x7seg;
体系结构x7seg的行为是
信号s：STD_LOGIC_VECTOR（1 downto 0）;
信号位：STD_LOGIC_VECTOR（3 downto 0）;
信号aen：STD_LOGIC_VECTOR（3 downto 0）;
开始
dp digit digit digit digit a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g a_to_g
变流器
实体BINtoBCD是
港口（
b：在STD_LOGIC_VECTOR（7 downto 0）;
p：out STD_LOGIC_VECTOR（9 downto 0）
）;
结束BINtoBCD;
建筑BINtoBCD的行为是
开始
bcdl：进程（b）
变量z：STD_LOGIC_VECTOR（17 downto 0）;
开始
因为我在0到17循环
z（i）：='0';
结束循环;
z（10 downto 3）：= b;
因为我在0到4循环
如果z（11 downto 8）> 4那么
z（11 downto 8）：= z（11 downto 8）+ 3;
万一;
如果z（15 downto 12）> 4那么
z（15 downto 12）：= z（15 downto 12）+ 3;
万一;
z（17 downto 1）：= z（16 downto 0）;
结束循环;
p
和顶级
实体BINtoBCD_Top是
港口（
mclk：在STD_LOGIC中;
clr：在STD_LOGIC中;
btn：在STD_LOGIC_VECTOR（3 downto 3）;
sw：在STD_LOGIC_VECTOR（7 downto 0）;
ld：out STD_LOGIC_VECTOR（7 downto 0）;
a_to_g：out STD_LOGIC_VECTOR（6 downto 0）;
an：out STD_LOGIC_VECTOR（3 downto 0）;
dp：输出STD_LOGIC
）;
结束BINtoBCD_Top;
体系结构BINtoBCD_Top的行为是
组件BINtoBCD是
港口（
b：在STD_LOGIC_VECTOR（7 downto 0）;
p：out STD_LOGIC_VECTOR（9 downto 0）
）;
最终组件;
组件x7seg是
港口（
x：在STD_LOGIC_VECTOR（15 downto 0）;
clk：在STD_LOGIC中;
clr：在STD_LOGIC中;
a_to_g：out STD_LOGIC_VECTOR（6 downto 0）;
an：out STD_LOGIC_VECTOR（3 downto 0）;
dp：输出STD_LOGIC
）;
最终组件;
组件ClkDiv
港口（
mclk：IN std_logic;
clr：IN std_logic;
clk：OUT std_logic
）;
结束组成部分;
信号时钟：STD_LOGIC;
信号x：STD_LOGIC_VECTOR（15 downto 0）;
信号p：STD_LOGIC_VECTOR（9 downto 0）;
开始
- 连接BINtoBCD的零和输出
x sw，
p => p
）;
X2：x7seg
港口地图（
x => x，
clk =>时钟，
clr => clr，
a_to_g => a_to_g，
an => an，
dp => dp
）;
X3：ClkDiv PORT MAP（
mclk => mclk，
clr => clr，
clk =>时钟
）;
结束行为;
时钟分频器已连接。
这段代码来自VHDL示例书，但我不能让这个代码工作。
什么缺少的想法？
clkdiv.vhd 2 KB



以下为原文

I am having a problem with a simple 8-bit input binary to bcd displaying to 7seg. I get the last number to display fine, but the first two remain dark.  For example 8-bit binary input of 11111111 should display 255 but I can only get the 5 to appear.
I have attached my current code. I thought at first that it was the clock but I cannot figure it out.
Here is the code for the Seven segment display:
entity x7seg isport(x: in STD_LOGIC_VECTOR(15 downto 0);clk : in STD_LOGIC;clr : in STD_LOGIC;a_to_g : out STD_LOGIC_VECTOR(6 downto 0);an : out STD_LOGIC_VECTOR(3 downto 0);dp : out STD_LOGIC);end x7seg;architecture Behavioral of x7seg is signal s: STD_LOGIC_VECTOR(1 downto 0); signal digit : STD_LOGIC_VECTOR(3 downto 0); signal aen : STD_LOGIC_VECTOR(3 downto 0);  begindp <= '1';-- set aen(3 downto 0) for leading blanksaen(3) <= x(15) or x(14) or x(13) or x(12);aen(2) <= x(15) or x(14) or x(13) or x(12)or x(11) or x(10) or x(9) or x(8);aen(1) <= x(15) or x(14) or x(13) or x(12)or x(11) or x(10) or x(9) or x(8)or x(7) or x(6) or x(5) or x(4);aen(0) <= '1'; -- digit 0 always on-- Quad 4-to-1 MUX: mux44process(s,x)begincase s is when "00" => digit <= x(3 downto 0);when "01" => digit <= x(7 downto 4);when "10" => digit <= x(11 downto 8);when others => digit <= x(15 downto 12);end case;end process;--// 7-segment decoder: hex7segprocess(digit)begincase digit is WHEN X"0" => a_to_g <= "0000001";  -- 0WHEN X"1" => a_to_g <= "1001111";  -- 1WHEN X"2" => a_to_g <= "0010010";  -- 2WHEN X"3" => a_to_g <= "0000110";  -- 3WHEN X"4" => a_to_g <= "1001100";  -- 4WHEN X"5" => a_to_g <= "0100100";  -- 5WHEN X"6" => a_to_g <= "1100000";  -- 6WHEN X"7" => a_to_g <= "0001111";  -- 7WHEN X"8" => a_to_g <= "0000000";  -- 8WHEN X"9" => a_to_g <= "0001100";  -- 9WHEN X"A" => a_to_g <= "0001000";  -- AWHEN X"B" => a_to_g <= "1100000";  -- BWHEN X"C" => a_to_g <= "0110001";  -- CWHEN X"D" => a_to_g <= "0100010";  -- DWHEN X"E" => a_to_g <= "0110000";  -- EWHEN others => a_to_g <= "0111000";  -- Fend case;end process;--Digit select: ancodeprocess(s, aen)begin an <= "1111";if aen(conv_integer(s)) = '1' thenan(conv_integer(s)) <= '0';end if;end process;-- 2-bit counterprocess(clk, clr)beginif clr = '1' then s <= "00";elsif clk'event and clk = '1' thens <= s+ 1;end if;end process; Converter
entity BINtoBCD isport(b : in STD_LOGIC_VECTOR(7 downto 0);p : out STD_LOGIC_VECTOR(9 downto 0) );end BINtoBCD;architecture Behavioral of BINtoBCD i***eginbcdl : process(b)variable z : STD_LOGIC_VECTOR(17 downto 0);beginfor i in 0 to 17 loopz(i) := '0';end loop;z(10 downto 3) := b;for i in 0 to 4 loopif z(11 downto 8) > 4 thenz(11 downto 8) := z(11 downto 8) + 3;end if;if z(15 downto 12) > 4 thenz(15 downto 12) := z(15 downto 12) + 3;end if;z(17 downto 1) := z(16 downto 0);end loop;p <= z(17 downto 8);end process bcdl;end Behavioral; and Top Level
entity BINtoBCD_Top isport(mclk : in STD_LOGIC;clr : in STD_LOGIC;btn : in STD_LOGIC_VECTOR(3 downto 3);sw : in STD_LOGIC_VECTOR(7 downto 0);ld : out STD_LOGIC_VECTOR(7 downto 0);a_to_g : out STD_LOGIC_VECTOR(6 downto 0);an : out STD_LOGIC_VECTOR(3 downto 0);dp : out STD_LOGIC);end BINtoBCD_Top;architecture Behavioral of BINtoBCD_Top iscomponent BINtoBCD isport(b : in STD_LOGIC_VECTOR(7 downto 0);p : out STD_LOGIC_VECTOR(9 downto 0));end component;component x7seg isport(x: in STD_LOGIC_VECTOR(15 downto 0);clk : in STD_LOGIC;clr : in STD_LOGIC;a_to_g : out STD_LOGIC_VECTOR(6 downto 0);an : out STD_LOGIC_VECTOR(3 downto 0);dp : out STD_LOGIC);end component;COMPONENT ClkDivPORT(mclk : IN std_logic;clr : IN std_logic;          clk : OUT std_logic);END COMPONENT;signal clock : STD_LOGIC;signal x : STD_LOGIC_VECTOR(15 downto 0);signal p : STD_LOGIC_VECTOR(9 downto 0);begin-- concatenate zeros and output of BINtoBCDx <= "000000" & p;-- display binary value of switches on LEDsld <= sw;B1: BINtoBCDport map(b => sw,p => p);X2: x7segport map(x => x,clk => clock,clr => clr,a_to_g => a_to_g,an => an,dp => dp);X3: ClkDiv PORT MAP(mclk => mclk,clr => clr,clk => clock);end Behavioral; The clock divider is attached.  This code is from a VHDL example book, I cannot, however, get this one to work. Any ideas what is missing?
            clkdiv.vhd ‏2 KB