如何进一步使用以上两个文件查看DSO上的输出？

嗨，
只是一个简短的回复（可能更明天）：
你的主板似乎是Spartan-3E入门套件。
这很重要，因为有更多的板可用于S3E设备。
如果您有不同的电路板，请纠正我。
请查看DAC的数据表。
我非常怀疑SPI接口将以50 MHz的SPI_CLK运行。
因此，虽然FPGA提供固定的50 MHz时钟，但您需要在FPGA内部减少这一点，以使SPI接口正常工作。
您获得的文件需要使用ISE软件进行处理。
您需要运行综合和实现步骤并生成用于配置FPGA的位文件。
这些基本步骤在ISE入门指南中进行了解释。
有一个很好的综合 
Eilert
在原帖中查看解决方案



以下为原文

Hi,
just a short reply (maybe more tomorrow)
:
Your board seems to be the Spartan-3E Starter Kit.
That's important, because there are many more boards available with a S3E Device.
So please correct me if you have a different board.
 
Please take a look at the datasheet of the DAC.
I have a strong doubt that the SPI interface will run with a SPI_CLK of 50 MHz. So, while the FPGA is supplied with the fixed 50 MHz clock, you need to reduce this inside the FPGA to get a working SPI interface up and running.
 
The Files you got need to be processed with the ISE software. You need to run the synthesis and implementation steps and generate a bitfile for configuring the FPGA. These basic steps are explained in teh ISE starter guide.
 
Have a nice synthesis
  Eilert
View solution in original post

嗨，
一些问题：
你有一个UCF文件？
哪个板？
您正在使用clk作为spi_clk。
SPI限制在几百千赫兹（可能是几兆赫兹，但附加设备设置限制），而大多数FPGA板的时钟频率在50到100 MHz之间。
你有另一个减少系统时钟的模块吗？
您正在使用狡猾的方案来序列化分配给“inter”的数据。
但是你有很多总是使用不同时钟信号的块。
模拟没有问题，但合成会有麻烦。
您生成的时钟信号不能放在全局时钟网络上（这在FPGA中也很少见），因此本地路由资源将被用于高偏斜和延迟。
大麻烦！
您应该了解如何使用时钟使能并使用相同的时钟信号触发所有进程。
有一个很好的综合 
Eilert



以下为原文

Hi,
some questions:
You have an UCF file? For which board?
 
You are using the clk as the spi_clk.
SPI is limited to some hundred kilohertz (maybe a few MHz, but the attached device sets the limit) while most FPGA Boards have clocks between 50 and 100 MHz.
Do you have another module that reduces the system clock?
 
You are using a cunning scheme to serialize the data assigned to "inter".
But you have many always blocks wich are using differnt clocking signals.
Simulation has no problem with that, but synthesis will have troubles.
The clock signals that you generate can not be put on global clock nets (which are also very rare in an FPGA), so local routing ressources will be used with high skew and delays. Big trouble!
 
You should learn about how to use clock enables and have all processes triggered with the same clock signal.
 
Have a nice synthesis
  Eilert
 

我为Spartan 3E创建了UCF文件（您可以在附件中看到）。
Spartan 3E的DAC可以支持最高50 MHz（我从用户指南中得到了这一点）。
嗨嘿，我可以知道为什么我应该减少我的系统时钟。
msgstr“”“您应该了解如何使用时钟启用并使用相同的时钟信号触发所有进程。”“”（如果不同进程需要不同的时钟信号，如何使用上述语句?????）
eilert，我能否回答我之前关于“如何使用以上两个文件进一步查看DSO输出”的帖子 
我还有一个问题，我应该在主模块中编写kcpsm3 verilog代码来处理SPARTAN 3E KIT ??? 
提前感谢你:-)
计数器UCF.ucf 1 KB



以下为原文

I have created UCF file  for Spartan 3E (You can see in the attachments) .
The DAC of Spartan 3E can support upto maximum of 50 MHz ( I got this point from User Guide) .
Hi eilert , May i know why i should reduce my system clock.?
"""You should learn about how to use clock enables and have all processes triggered with the same clock signal."""( If different processes need different clock signals how can use the above statement?????)
 
eilert, can i get answer for my previous post regarding "how to proceed further to see the output on DSO using above two files"
         

I have one more question that should i write kcpsm3 verilog code in the main module to work on SPARTAN 3E KIT???

          Thanking you in advance :-)

            Counter UCF.ucf ‏1 KB

嗨，
只是一个简短的回复（可能更明天）：
你的主板似乎是Spartan-3E入门套件。
这很重要，因为有更多的板可用于S3E设备。
如果您有不同的电路板，请纠正我。
请查看DAC的数据表。
我非常怀疑SPI接口将以50 MHz的SPI_CLK运行。
因此，虽然FPGA提供固定的50 MHz时钟，但您需要在FPGA内部减少这一点，以使SPI接口正常工作。
您获得的文件需要使用ISE软件进行处理。
您需要运行综合和实现步骤并生成用于配置FPGA的位文件。
这些基本步骤在ISE入门指南中进行了解释。
有一个很好的综合 
Eilert



以下为原文

Hi,
just a short reply (maybe more tomorrow)
:
Your board seems to be the Spartan-3E Starter Kit.
That's important, because there are many more boards available with a S3E Device.
So please correct me if you have a different board.
 
Please take a look at the datasheet of the DAC.
I have a strong doubt that the SPI interface will run with a SPI_CLK of 50 MHz. So, while the FPGA is supplied with the fixed 50 MHz clock, you need to reduce this inside the FPGA to get a working SPI interface up and running.
 
The Files you got need to be processed with the ISE software. You need to run the synthesis and implementation steps and generate a bitfile for configuring the FPGA. These basic steps are explained in teh ISE starter guide.
 
Have a nice synthesis
  Eilert

priya.302写道：
我为Spartan 3E创建了UCF文件（您可以在附件中看到）。
Spartan 3E是一个FPGA系列。
它不是董事会。
它甚至不是特定的设备。
----------------------------是的，我这样做是为了谋生。



以下为原文

priya.302 wrote:
I have created UCF file  for Spartan 3E (You can see in the attachments) .

Spartan 3E is an FPGA family. It is not a board. It is not even a specific device.
----------------------------Yes, I do this for a living.

我正在处理Spartan-3E入门套件。
谢谢你eilert你告诉我有一个S3E设备有更多的板可用的信息，以前我没有意识到这一点。
我已经浏览了DAC的数据表（第69页（http://web.iitd.ac.in/~shouri/eep201/ug230.pdf），因为PDF大小超过5 MB，因此我无法保持
在附件中）我做了综合，实现和我也生成了BIT文件，之后我用iMPACT使用BIT文件重新配置FPGA（XC3S500E），但我无法在DSO上看到输出。
摆脱这个问题我需要帮助。



以下为原文

Ya i am dealing with Spartan-3E Starter Kit. Thank you eilert you gave me the info that there are many more boards available with a S3E Device, previously i was unaware of this.
 I have gone through the datasheet of the DAC (Page no 69 (http://web.iitd.ac.in/~shouri/eep201/ug230.pdf) as the PDF size is more than 5 MB so i am unbale to keep in attachments)  i did synthesis , Implementation and I generated BIT file too, after this  i used iMPACT to reconfigure the FPGA (XC3S500E) using BIT file but i am unable to see outputs on DSO. I need help in getting out of thisproblem.
 

嗨，
所以你现在处于“流动”状态，很棒。
:-)
我希望你接受了pg的建议。
UG230的70/71，用于禁用其他SPI设备。
我也看了一下DAC数据表。
我很惊讶它实际上可以处理SCK输入上的50 MHz。
（根据DAC数据表第10页的图1）
但是，这并不能保证实际的实现会起作用。
除了确定最小时钟周期的t3和t4之外，还要考虑t1和t2。
这些指定了SDI不能改变的建立/保持窗口，永远不会！
我想知道你是否已经努力将SPI_CLK的上升沿放在SDI的中间。
我想知道综合如何将clk放到SPI_CLK中。
这通常会导致一些问题，因为全局时钟网络和其他路由资源之间没有直接连接。
你现在应该做的事情是：
检查综合报告中的警告和信息。
您还可以在那里找到一些时序信息，指出设计的关键路径。
（这里，输出延迟会很有趣。）
有关输出延迟的更准确信息可以在静态时序分析报告中找到，或者与fpga_editor交互式地找到。
然后，由于您手头有DSO，您可以同时查看DAC SCK和SDI引脚。
您可以找到一个不错的触发点或单次尝试运气，确认满足设置/保持条件并且信号看起来很好（没有尖峰等）。
________________________
既然你提到了Picoblaze。
在这里您可以找到S3E入门套件的一些参考设计：
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
还有DAC设计。
通过研究设计文档中给出的解释，您将获得许多有用的提示。
即使你不打算使用picoblaze，这可能会有用。
此外，您可以简单地实现参考设计，只是为了确保您的电路板和DAC正常工作。
一旦您在DAC输出上看到一些信号，您就可以查看SPI信号，以了解它们在工作设计中的外观。
_________________
最后要提到的是：你做过模拟吗？
应始终进行行为模拟，但在您的情况下，非常推荐使用后标准模拟。
试一试。
有一个很好的综合 
Eilert



以下为原文

Hi,
so you are in the "Flow" now, great. :-)
 
I hope you folowed the advice from pg. 70/71 of UG230, to disable the other SPI devices.
 
I took a look at the DAC datasheet too.
I'm very surprised that it actually can handle 50 MHz on the SCK input.
(According to Figure 1 on pg. 10 of the DAC datasheet)
However, this is no guarantee that an actual implementation will work.
Besides t3 and t4 which determine the minimum clock period, there are also t1 and t2 to be considered.
These specify the setup/hold window where SDI must not change, never ever!
I wonder if you made any effort to put the rising edge of SPI_CLK in the middle of SDI.
 
I wonder how the synthesis put clk to SPI_CLK. This normally  leads to some problems, because there's no direct connection between global clock nets and other routing ressources.
 
Things you should do now are these:
Check the synthesis report for warnings and infos.
You also find some timing informations there, indicatinǵ the critical paths of the design.
(Here, the output Delays would be interesting.)
More accurate information about the output delays can be found in the static timing analysis report or interactively with the fpga_editor.
 
Then, since you have a DSO at hand, you may take a look at the DACs SCK and SDI pins simultaneously.
Wether you find a nice trigger point or try your luck with single shots, verify that the setup/hold conditions are met and the signals look good (no spikes etc.).

________________________
 
Since you mentioned the Picoblaze.
Here you find some reference designs for the S3E starter kit:
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
 
There is a DAC design too.
You will get many useful hints by studying the explanations given in the design documentation.
Even if you are not going to use the picoblaze this might be useful.
 
Also, you can simply implement the reference design, just to make sure your board and DAC work correctly.
Once you happen to see some signals on the DAC output, you can take a look at the SPI signals to get an idea of how they have to look like for a working design.
 
_________________
 
Last thing to mention: Have you made simulations?
A behavioral simulation should always be done, but in your case a post-par simulation would be very recommendable.
Give it a try.
 
Have a nice synthesis
  Eilert
 
 
 
 
 
 

我已经看过参考设计，看到这个例子我怀疑我应该在主模块中使用KCPSM3程序???
我可以知道我应该考虑t1和t2吗？
你能建议我如何把SPI_CLK的上升沿放在SDI的中间。
我们可以写那样的代码吗???
合成后我没有收到任何警告和错误，我在附件中发送综合报告。
我有一个疑问，我应该在生成BIT文件之前在主模块中包含KCPSM3 verilog程序???  
感谢你的支持。



以下为原文

I have gone through the Reference designs , after seeing the example i got a doubt that should i use KCPSM3 program  in the main module ???
May i know whi should i consider t1 and t2??
Can you suggest me how to put the rising edge of SPI_CLK in the middle of SDI.??? Can we write the code like that???
I didn't get any warnings and errors after synthesis, i am sending the synthesis report in the attachments.
 
I have one doubt that should i include KCPSM3 verilog Program in the main module before generating BIT file???
         
                  Thnak you eilert for your support.

嗨，
关于t1＆amp; t2：
你不知道FF的设置和保持时间吗？
忽略这可能会导致亚稳态，因此设备将无法正常工作。
为了在SCI的稳定区域中获得SCK的上升沿，可以使用许多方法。
这取决于您的设计哪一个以最少的努力为您服务。
一种非常简单的方法是使用反相时钟信号作为SPI时钟。
其他方法可以包括DCM以生成相移时钟
或更快的时钟（* 2）将risinig边缘放在所需的位置。
参考设计：
这可以自己运行，那时你不需要你的设计。
这只是为了看到一些类似的设计工作。
您还可以检查几个先决条件。
（例如，如果禁用其他SPI设备的方式与您完成的方式相同）
但是，一旦运行，您还可以选择更改picoblaze的汇编程序，因此它会计算三角波的值并将它们发送到DAC。
但如果您喜欢纯硬件解决方案，则无需使用Picoblaze。
由于您似乎是初学者，因此您应该学习更多有关FPGA和同步设计技术的知识。
有一个很好的综合 
Eilert



以下为原文

Hi,
about t1&t2:
Don't you know about setup and hold times of FFs?
Ignoring this can cause metastabilities so the device won't work correctly.
 
To get the rising edge of SCK in a stable region of SDI a number of approaches can be used.
It depends on your design which one serves you best with the least effort.
One very simple approach would be to use an inverted clock signal as the SPI clock.
Other approaches can include DCMs to generate phase shifted clocks
or faster clocks (*2) to put the risinig edge at the desired position. 
 
 
The reference design:
This can run of it's own, you don't need your design at that moment.
It is just meant to see some similar design working. 
Also you can check several prerequisites. (e.g. if the disabling of the other SPI devices is correct the way you've done it)
However, once you got this running, you can also choose to change the assembler program of the picoblaze, so it calculates the values for your triangle wave and sends these to the DAC.
 
But if you prefere a pure hardware solution, there's no need to use the Picoblaze.
Since you seem to be a beginner, you should learn a little more about FPGAs and synchronous design techniques.
 
 
Have a nice synthesis
   Eilert

我知道设置时间，保持时间，最小和最大延迟约束，我们可以口头说这些东西，但我在困境中如何为他们编写代码。
从上一篇文章中你的意思是在主模块中不需要KCPSM3 verilog程序????
最后，现在我很困惑如何进一步看到DSO的波澜。



以下为原文

I know about setup time , hold time , min and max delay constraints, we can say orally these things but i am in dilema how to write the code for them.
from the previous post do you mean no need of KCPSM3 verilog program in the main module????
Finally now i am in confusion how to move further to see waves on DSO.